Fix tricore python binding

- fix HACK.TXT

CREDITS.TXT

@@ -87,3 +87,4 @@ david942j: BPF (both classic and extended) architecture.
 fanfuqiang & citypw & porto703 : RISCV architecture.
 Josh "blacktop" Maine: Arm64 architecture improvements.
 Finn Wilkinson: AArch64 update to Armv9.2-a (SME + SVE2 support)
+Billow & Sidneyp : TriCore architecture.

HACK.TXT

@@ -14,11 +14,13 @@ Capstone source is organized as followings.
 │   ├── Mips        <- Mips engine
 │   ├── MOS65XX     <- MOS65XX engine
 │   ├── PowerPC     <- PowerPC engine
-│   ├── Sparc       <- Sparc engine
-│   ├── SystemZ     <- SystemZ engine
-│   ├── TMS320C64x  <- TMS320C64x engine
-│   ├── X86         <- X86 engine
-│   └── XCore       <- XCore engine
+│   ├── RISCV <- RISCV engine
+│   ├── SH <- SH engine
+│   ├── Sparc      <- Sparc engine
+│   ├── SystemZ    <- SystemZ engine
+│   ├── TMS320C64x <- TMS320C64x engine
+│   ├── TriCore <- TriCore engine
+│   ├── WASM  <- WASM engine
 ├── bindings        <- all bindings are under this dir
 │   ├── java        <- Java bindings + test code
 │   ├── ocaml       <- Ocaml bindings + test code
@@ -85,7 +87,7 @@ Tests:
 - tests/test_detail.c
 - tests/test_iter.c
 - tests/test_newarch.c
-- suite/fuzz/fuzz_disasm.c: add the architecture and its modes to the list of fuzzed platforms
+- suite/fuzz/platform.c: add the architecture and its modes to the list of fuzzed platforms
 - suite/capstone_get_setup.c
 - suite/MC/newarch/mode.mc: samples
 - suite/test_corpus.py: correspondence between architecture and mode as text and architecture number for fuzzing

Makefile

@@ -307,18 +307,13 @@ ifneq (,$(findstring bpf,$(CAPSTONE_ARCHS)))
 endif
 
 DEP_TRICORE =
-DEP_TRICORE += arch/TriCore/TriCoreGenAsmWriter.inc
-DEP_TRICORE += arch/TriCore/TriCoreGenInstrInfo.inc
-DEP_TRICORE += arch/TriCore/TriCoreGenDisassemblerTables.inc
-DEP_TRICORE += arch/TriCore/TriCoreGenRegisterInfo.inc
+DEP_TRICORE +=$(wildcard arch/TriCore/TriCore*.inc)
 
 LIBOBJ_TRICORE =
 ifneq (,$(findstring tricore,$(CAPSTONE_ARCHS)))
 	CFLAGS += -DCAPSTONE_HAS_TRICORE
-	LIBOBJ_TRICORE += $(OBJDIR)/arch/TriCore/TriCoreDisassembler.o
-	LIBOBJ_TRICORE += $(OBJDIR)/arch/TriCore/TriCoreInstPrinter.o
-	LIBOBJ_TRICORE += $(OBJDIR)/arch/TriCore/TriCoreMapping.o
-	LIBOBJ_TRICORE += $(OBJDIR)/arch/TriCore/TriCoreModule.o
+	LIBSRC_TRICORE += $(wildcard arch/TriCore/TriCore*.c)
+	LIBOBJ_TRICORE += $(LIBSRC_TRICORE:%.c=$(OBJDIR)/%.o)
 endif
 
 

bindings/python/capstone/__init__.py

@@ -383,7 +383,7 @@ def copy_ctypes_list(src):
     return [copy_ctypes(n) for n in src]
 
 # Weird import placement because these modules are needed by the below code but need the above functions
-from . import arm, arm64, m68k, mips, ppc, sparc, systemz, x86, xcore, tms320c64x, m680x, evm, mos65xx, bpf, riscv
+from . import arm, arm64, m68k, mips, ppc, sparc, systemz, x86, xcore, tms320c64x, m680x, evm, mos65xx, bpf, riscv, tricore
 
 class _cs_arch(ctypes.Union):
     _fields_ = (
@@ -402,6 +402,7 @@ class _cs_arch(ctypes.Union):
         ('mos65xx', mos65xx.CsMOS65xx),
         ('bpf', bpf.CsBPF),
         ('riscv', riscv.CsRISCV),
+        ('tricore', tricore.CsTriCore),
     )
 
 class _cs_detail(ctypes.Structure):
@@ -725,6 +726,8 @@ def __gen_detail(self):
             (self.operands) = bpf.get_arch_info(self._raw.detail.contents.arch.bpf)
         elif arch == CS_ARCH_RISCV:
             (self.operands) = riscv.get_arch_info(self._raw.detail.contents.arch.riscv)
+        elif arch == CS_ARCH_TRICORE:
+            (self.operands) = riscv.get_arch_info(self._raw.detail.contents.arch.tricore)
 
 
     def __getattr__(self, name):

bindings/python/capstone/tricore.py

@@ -0,0 +1,45 @@
+# Capstone Python bindings, by billow <[email protected]>
+
+import ctypes, copy
+from .tricore_const import *
+
+class TriCoreOpMem(ctypes.Structure):
+    _fields_ = (
+        ('base', ctypes.c_uint8),
+        ('disp', ctypes.c_int32),
+    )
+
+
+class TriCoreOpValue(ctypes.Union):
+    _fields_ = (
+        ('reg', ctypes.c_uint),
+        ('imm', ctypes.c_int32),
+        ('mem', TriCoreOpMem),
+    )
+
+
+class TriCoreOp(ctypes.Structure):
+    _fields_ = (
+        ('type', ctypes.c_uint),
+        ('value', TriCoreOpValue),
+    )
+
+    @property
+    def imm(self):
+        return self.value.imm
+
+    @property
+    def reg(self):
+        return self.value.reg
+
+    @property
+    def mem(self):
+        return self.value.mem
+
+
+# Instruction structure
+class CsTriCore(ctypes.Structure):
+    _fields_ = (
+        ('op_count', ctypes.c_uint8),
+        ('operands', TriCoreOp * 8),
+    )

bindings/python/test_tricore.py

@@ -0,0 +1,65 @@
+#!/usr/bin/env python
+
+# Capstone Python bindings, by Nguyen Anh Quynnh <[email protected]>
+
+from __future__ import print_function
+from capstone import *
+from capstone.tricore import *
+from xprint import to_x, to_hex
+
+TRICORE_CODE = b"\x16\x01\x20\x01\x1d\x00\x02\x00\x8f\x70\x00\x11\x40\xae\x89\xee\x04\x09\x42\xf2\xe2\xf2\xc2\x11\x19" \
+               b"\xff\xc0\x70\x19\xff\x20\x10"
+
+all_tests = (
+    (CS_ARCH_TRICORE, CS_MODE_TRICORE_162, TRICORE_CODE, "TriCore"),
+)
+
+
+def print_insn_detail(insn):
+    # print address, mnemonic and operands
+    print("0x%x:\t%s\t%s" % (insn.address, insn.mnemonic, insn.op_str))
+
+    # "data" instruction generated by SKIPDATA option has no detail
+    if insn.id == 0:
+        return
+
+    if len(insn.operands) > 0:
+        print("\top_count: %u" % len(insn.operands))
+        c = 0
+        for i in insn.operands:
+            if i.type == TRICORE_OP_REG:
+                print("\t\toperands[%u].type: REG = %s" % (c, insn.reg_name(i.reg)))
+            if i.type == TRICORE_OP_IMM:
+                print("\t\toperands[%u].type: IMM = 0x%s" % (c, to_x(i.imm)))
+            if i.type == TRICORE_OP_MEM:
+                print("\t\toperands[%u].type: MEM" % c)
+                if i.mem.base != 0:
+                    print("\t\t\toperands[%u].mem.base: REG = %s" \
+                          % (c, insn.reg_name(i.mem.base)))
+                if i.mem.disp != 0:
+                    print("\t\t\toperands[%u].mem.disp: 0x%s" \
+                          % (c, to_x(i.mem.disp)))
+            c += 1
+
+
+# ## Test class Cs
+def test_class():
+    for (arch, mode, code, comment) in all_tests:
+        print("*" * 16)
+        print("Platform: %s" % comment)
+        print("Code: %s" % to_hex(code))
+        print("Disasm:")
+
+        try:
+            md = Cs(arch, mode)
+            md.detail = True
+            for insn in md.disasm(code, 0x1000):
+                print_insn_detail(insn)
+                print()
+                print("0x%x:\n" % (insn.address + insn.size))
+        except CsError as e:
+            print("ERROR: %s" % e)
+
+
+if __name__ == '__main__':
+    test_class()

suite/capstone_get_setup.c

@@ -70,6 +70,9 @@ int main()
 	if (cs_support(CS_SUPPORT_X86_REDUCE)) {
 		printf("x86_reduce=1 ");
 	}
+	if (cs_support(CS_ARCH_TRICORE)) {
+		printf("tricore=1 ");
+	}
 	printf("\n");
 
 	return 0;