Upper all inc and fix

capstone-engine · May 1, 2023 · 985b6fc · 985b6fc
1 parent 620f0d0
commit 985b6fc
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Showing 17 changed files with 7,968 additions and 7,865 deletions.
diff --git a/arch/TriCore/TriCoreDisassembler.c b/arch/TriCore/TriCoreDisassembler.c
@@ -189,25 +189,25 @@ bool TriCore_getFeatureBits(unsigned int mode, unsigned int feature)
 {
 	switch (mode) {
 	case CS_MODE_TRICORE_110: {
-		return feature == TriCore_HasV110Ops;
+		return feature == TRICORE_HasV110Ops;
 	}
 	case CS_MODE_TRICORE_120: {
-		return feature == TriCore_HasV120Ops;
+		return feature == TRICORE_HasV120Ops;
 	}
 	case CS_MODE_TRICORE_130: {
-		return feature == TriCore_HasV130Ops;
+		return feature == TRICORE_HasV130Ops;
 	}
 	case CS_MODE_TRICORE_131: {
-		return feature == TriCore_HasV131Ops;
+		return feature == TRICORE_HasV131Ops;
 	}
 	case CS_MODE_TRICORE_160: {
-		return feature == TriCore_HasV160Ops;
+		return feature == TRICORE_HasV160Ops;
 	}
 	case CS_MODE_TRICORE_161: {
-		return feature == TriCore_HasV161Ops;
+		return feature == TRICORE_HasV161Ops;
 	}
 	case CS_MODE_TRICORE_162: {
-		return feature == TriCore_HasV162Ops;
+		return feature == TRICORE_HasV162Ops;
 	}
 	default:
 		return false;
@@ -512,13 +512,13 @@ static DecodeStatus DecodeBOLInstruction(MCInst *Inst, unsigned Insn,
 	const MCInstrDesc *desc = &TriCoreInsts[MCInst_getOpcode(Inst)];
 
 	switch (MCInst_getOpcode(Inst)) {
-	case TriCore_LD_A_bol:
-	case TriCore_LD_B_bol:
-	case TriCore_LD_BU_bol:
-	case TriCore_LD_H_bol:
-	case TriCore_LD_HU_bol:
-	case TriCore_LD_W_bol:
-	case TriCore_LEA_bol: {
+	case TRICORE_LD_A_bol:
+	case TRICORE_LD_B_bol:
+	case TRICORE_LD_BU_bol:
+	case TRICORE_LD_H_bol:
+	case TRICORE_LD_HU_bol:
+	case TRICORE_LD_W_bol:
+	case TRICORE_LEA_bol: {
 		// Decode s1_d.
 		status = DecodeRegisterClass(Inst, s1_d, &desc->OpInfo[0],
 					     Decoder);
@@ -532,10 +532,10 @@ static DecodeStatus DecodeBOLInstruction(MCInst *Inst, unsigned Insn,
 			return status;
 		break;
 	}
-	case TriCore_ST_A_bol:
-	case TriCore_ST_B_bol:
-	case TriCore_ST_H_bol:
-	case TriCore_ST_W_bol: {
+	case TRICORE_ST_A_bol:
+	case TRICORE_ST_B_bol:
+	case TRICORE_ST_H_bol:
+	case TRICORE_ST_W_bol: {
 		// Decode s2.
 		status = DecodeRegisterClass(Inst, s2, &desc->OpInfo[0],
 					     Decoder);
@@ -698,7 +698,7 @@ static DecodeStatus DecodeRRInstruction(MCInst *Inst, unsigned Insn,
 	if (desc->NumOperands == 1) {
 		if (desc->OpInfo[0].OperandType == MCOI_OPERAND_REGISTER) {
 			switch (MCInst_getOpcode(Inst)) {
-			case TriCore_CALLI_rr_v110: {
+			case TRICORE_CALLI_rr_v110: {
 				return DecodeRegisterClass(
 					Inst, s2, &desc->OpInfo[0], Decoder);
 			}
@@ -1308,7 +1308,7 @@ static DecodeStatus DecodeBRRInstruction(MCInst *Inst, unsigned Insn,
 		return MCDisassembler_Fail;
 
 	const MCInstrDesc *desc = &TriCoreInsts[MCInst_getOpcode(Inst)];
-	if (MCInst_getOpcode(Inst) == TriCore_LOOP_brr) {
+	if (MCInst_getOpcode(Inst) == TRICORE_LOOP_brr) {
 		status = DecodeRegisterClass(Inst, s2, &desc->OpInfo[0],
 					     Decoder);
 		if (status != MCDisassembler_Success)

diff --git a/arch/TriCore/TriCoreGenAsmWriter.inc b/arch/TriCore/TriCoreGenAsmWriter.inc
@@ -1,9 +1,16 @@
 /* Capstone Disassembly Engine, http://www.capstone-engine.org */
 /* By Nguyen Anh Quynh <[email protected]>, 2013-2022, */
 /*    Rot127 <[email protected]> 2022-2023 */
-/* Automatically generated file by the LLVM TableGen Disassembler Backend. */
+/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */
+
+/* LLVM-commit: <commit> */
+/* LLVM-tag: <tag> */
+
 /* Do not edit. */
 
+/* Capstone's LLVM TableGen Backends: */
+/* https://github.com/capstone-engine/llvm-capstone */
+
 #include <capstone/platform.h>
 #include <assert.h>
 
@@ -471,6 +478,7 @@ MnemonicBitsInfo getMnemonic(MCInst *MI, SStream *O) {
     2817U,	// PATCHABLE_EVENT_CALL
     2793U,	// PATCHABLE_TYPED_EVENT_CALL
     0U,	// ICALL_BRANCH_FUNNEL
+    0U,	// MEMBARRIER
     0U,	// G_ASSERT_SEXT
     0U,	// G_ASSERT_ZEXT
     0U,	// G_ASSERT_ALIGN
@@ -532,6 +540,8 @@ MnemonicBitsInfo getMnemonic(MCInst *MI, SStream *O) {
     0U,	// G_ATOMICRMW_FSUB
     0U,	// G_ATOMICRMW_FMAX
     0U,	// G_ATOMICRMW_FMIN
+    0U,	// G_ATOMICRMW_UINC_WRAP
+    0U,	// G_ATOMICRMW_UDEC_WRAP
     0U,	// G_FENCE
     0U,	// G_BRCOND
     0U,	// G_BRINDIRECT
@@ -1746,6 +1756,7 @@ MnemonicBitsInfo getMnemonic(MCInst *MI, SStream *O) {
     0U,	// PATCHABLE_EVENT_CALL
     0U,	// PATCHABLE_TYPED_EVENT_CALL
     0U,	// ICALL_BRANCH_FUNNEL
+    0U,	// MEMBARRIER
     0U,	// G_ASSERT_SEXT
     0U,	// G_ASSERT_ZEXT
     0U,	// G_ASSERT_ALIGN
@@ -1807,6 +1818,8 @@ MnemonicBitsInfo getMnemonic(MCInst *MI, SStream *O) {
     0U,	// G_ATOMICRMW_FSUB
     0U,	// G_ATOMICRMW_FMAX
     0U,	// G_ATOMICRMW_FMIN
+    0U,	// G_ATOMICRMW_UINC_WRAP
+    0U,	// G_ATOMICRMW_UDEC_WRAP
     0U,	// G_FENCE
     0U,	// G_BRCOND
     0U,	// G_BRINDIRECT

diff --git a/arch/TriCore/TriCoreGenCSFeatureName.inc b/arch/TriCore/TriCoreGenCSFeatureName.inc
@@ -1,16 +1,22 @@
-/* Capstone Disassembly Engine, https://www.capstone-engine.org */
-/* By Nguyen Anh Quynh <[email protected]>, 2013-2019 */
-/* By Rot127 <[email protected]>, 2023 */
+/* Capstone Disassembly Engine, http://www.capstone-engine.org */
+/* By Nguyen Anh Quynh <[email protected]>, 2013-2022, */
+/*    Rot127 <[email protected]> 2022-2023 */
+/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */
 
-/* Auto generated file. Do not edit. */
-/* Code generator: https://github.com/capstone-engine/capstone/tree/next/suite/auto-sync */
+/* LLVM-commit: <commit> */
+/* LLVM-tag: <tag> */
 
-{ TriCore_FEATURE_HasV110, "HasV110" },
-{ TriCore_FEATURE_HasV120_UP, "HasV120_UP" },
-{ TriCore_FEATURE_HasV130_UP, "HasV130_UP" },
-{ TriCore_FEATURE_HasV161, "HasV161" },
-{ TriCore_FEATURE_HasV160_UP, "HasV160_UP" },
-{ TriCore_FEATURE_HasV131_UP, "HasV131_UP" },
-{ TriCore_FEATURE_HasV161_UP, "HasV161_UP" },
-{ TriCore_FEATURE_HasV162, "HasV162" },
-{ TriCore_FEATURE_HasV162_UP, "HasV162_UP" },
+/* Do not edit. */
+
+/* Capstone's LLVM TableGen Backends: */
+/* https://github.com/capstone-engine/llvm-capstone */
+
+{ TRICORE_FEATURE_HasV110, "HasV110" },
+{ TRICORE_FEATURE_HasV120_UP, "HasV120_UP" },
+{ TRICORE_FEATURE_HasV130_UP, "HasV130_UP" },
+{ TRICORE_FEATURE_HasV161, "HasV161" },
+{ TRICORE_FEATURE_HasV160_UP, "HasV160_UP" },
+{ TRICORE_FEATURE_HasV131_UP, "HasV131_UP" },
+{ TRICORE_FEATURE_HasV161_UP, "HasV161_UP" },
+{ TRICORE_FEATURE_HasV162, "HasV162" },
+{ TRICORE_FEATURE_HasV162_UP, "HasV162_UP" },