riscv64: Support scalar-vector bitcasts #8692
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This was accidentally broken in bytecodealliance#8692. It turns out bitcasts from i128 to i128 are legal, that PR accidentally reverted that use case. This is now added to a runtest to ensure it works on all platforms.
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This was accidentally broken in bytecodealliance#8692. It turns out bitcasts from i128 to i128 are legal, that PR accidentally reverted that use case. This is now added to a runtest to ensure it works on all platforms.
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This was accidentally broken in #8692. It turns out bitcasts from i128 to i128 are legal, that PR accidentally reverted that use case. This is now added to a runtest to ensure it works on all platforms.
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👋 Hey,
This PR Implements lowerings for casting between scalar types and vector types. This is split between two implementations.
For i128 to 128bit vectors, we have lowerings that correctly split or join the high and low halves.
Additionally, the RISC-V backend fully supports smaller (and larger) vectors, so for vectors 64bit or smaller, we also implement single instruction lowerings to move Vectors to the X and F registers, and vice-versa.
Bitcasting between larger vectors types should already be supported, since we don't actually need to do anything to the register.
cc: #6104