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[patch-axel-26] inline RESET_CYCLES #125

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[patch-axel-26] inline RESET_CYCLES #125

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e022bef
risc-v: make initTimer() call resetTimer()
axel-h May 30, 2022
db552d4
risc-v: inline RESET_CYCLES
axel-h May 2, 2023
280737d
wip debug QEMU reset issues
axel-h Nov 29, 2023
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31 changes: 19 additions & 12 deletions src/arch/riscv/machine/hardware.c
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Original file line number Diff line number Diff line change
Expand Up @@ -13,10 +13,6 @@
#include <arch/machine.h>
#include <arch/smp/ipi.h>

#ifndef CONFIG_KERNEL_MCS
#define RESET_CYCLES ((TIMER_CLOCK_HZ / MS_IN_S) * CONFIG_TIMER_TICK_MS)
#endif /* !CONFIG_KERNEL_MCS */

#define IS_IRQ_VALID(X) (((X)) <= maxIRQ && (X) != irqInvalid)

word_t PURE getRestartPC(tcb_t *thread)
Expand Down Expand Up @@ -224,21 +220,32 @@ static inline void ackInterrupt(irq_t irq)
#ifndef CONFIG_KERNEL_MCS
void resetTimer(void)
{
uint64_t target;
// repeatedly try and set the timer in a loop as otherwise there is a race and we
// may set a timeout in the past, resulting in it never getting triggered
do {
target = riscv_read_time() + RESET_CYCLES;
sbi_set_timer(target);
} while (riscv_read_time() > target);
/* timer must be > 1 kHz */
SEL4_COMPILE_ASSERT(timer_clock_1mhz, TIMER_CLOCK_HZ > 1000);
const uint64_t ticks_per_ms = TIMER_CLOCK_HZ / MS_IN_S;
const uint64_t delta = ticks_per_ms * CONFIG_TIMER_TICK_MS;
uint64_t target = riscv_read_time() + delta;
sbi_set_timer(target);
#if defined(CONFIG_PLAT_QEMU_RISCV_VIRT) || defined(CONFIG_PLAT_SPIKE)
/* Perform a sanity check that the margin is big enough that we end up
* with a timestamp in the future. Seems it happened in QEMU that the
* simulation was too slow.
*/
uint64_t now = riscv_read_time();
if (likely(now >= target)) {
printf("Timer reset failed, %"PRIu64" (now) >= %"PRIu64"\n", now, target);
fail("Timer reset failed");
UNREACHABLE();
}
#endif
}

/**
DONT_TRANSLATE
*/
BOOT_CODE void initTimer(void)
{
sbi_set_timer(riscv_read_time() + RESET_CYCLES);
resetTimer();
}
#endif /* !CONFIG_KERNEL_MCS */

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