WIP vspace/arm32 merge code blocks

src/arch/arm/32/kernel/vspace.c

@@ -540,54 +540,44 @@ BOOT_CODE cap_t create_mapped_it_frame_cap(cap_t pd_cap, pptr_t pptr, vptr_t vpt
     return cap;
 }
 
-#ifndef CONFIG_ARM_HYPERVISOR_SUPPORT
-
-BOOT_CODE void activate_kernel_vspace(void)
-{
-    /* Ensure that there's nothing stale in newly-mapped regions, and
-       that everything we've written (particularly the kernel page tables)
-       is committed. */
-    cleanInvalidateL1Caches();
-    setCurrentPD(addrFromKPPtr(armKSGlobalPD));
-    invalidateLocalTLB();
-    lockTLBEntry(PPTR_BASE);
-    lockTLBEntry(PPTR_VECTOR_TABLE);
-}
 
-#else
 
 BOOT_CODE void activate_kernel_vspace(void)
 {
-    uint32_t r;
     /* Ensure that there's nothing stale in newly-mapped regions, and
        that everything we've written (particularly the kernel page tables)
        is committed. */
     cleanInvalidateL1Caches();
+
+#ifdef CONFIG_ARM_HYPERVISOR_SUPPORT
     /* Setup the memory attributes: We use 2 indicies (cachable/non-cachable) */
     setHMAIR((ATTRINDX_NONCACHEABLE << 0) | (ATTRINDX_CACHEABLE << 8), 0);
     setCurrentHypPD(addrFromKPPtr(armHSGlobalPGD));
     invalidateHypTLB();
-#if 0 /* Can't lock entries on A15 */
+    /* TODO find a better place to init the VMMU */
+    setVTCR(
+        /* [0:3] T0SZ = 0 to use range 2^32
+         * [4]: Sign extension bit, must be set to T0SZ[3]
+         * [5]: ???
+         * [6:7]: SL0 = b00 (Start at second level)
+         */
+        BIT(8) /* Inner write-back, write-allocate */
+        | BIT(10) /* Outer write-back, write-allocate */
+        | BIT(31) /* Long descriptor format (not that we have a choice) */
+    );
+#else /* not CONFIG_ARM_HYPERVISOR_SUPPORT */
+    setCurrentPD(addrFromKPPtr(armKSGlobalPD));
+    invalidateLocalTLB();
+
+    /* ToDo: cleanup this TLB entry lock down hack? It's not supported by ARMv8
+     *       and on ARMv7 we are doing this only if not HYP - because A15 does
+     *       not support it?
+     */
     lockTLBEntry(PPTR_BASE);
     lockTLBEntry(PPTR_VECTOR_TABLE);
-#endif
-    /* TODO find a better place to init the VMMU */
-    r = 0;
-    /* Translation range */
-    r |= (0x0 << 0);     /* 2^(32 -(0)) input range. */
-    r |= (r & 0x8) << 1; /* Sign bit */
-    /* starting level */
-    r |= (0x0 << 6);     /* Start at second level */
-    /* Sharability of tables */
-    r |= BIT(8);       /* Inner write-back, write-allocate */
-    r |= BIT(10);      /* Outer write-back, write-allocate */
-    /* Long descriptor format (not that we have a choice) */
-    r |= BIT(31);
-    setVTCR(r);
+#endif /* [not] CONFIG_ARM_HYPERVISOR_SUPPORT */
 }
 
-#endif /* CONFIG_ARM_HYPERVISOR_SUPPORT */
-
 BOOT_CODE void write_it_asid_pool(cap_t it_ap_cap, cap_t it_pd_cap)
 {
     asid_pool_t *ap = ASID_POOL_PTR(pptr_of_cap(it_ap_cap));