Update comments to address feedback in Rahix#562

armandas · Oct 5, 2024 · 8c4ca6f · 8c4ca6f
1 parent 97312b0
commit 8c4ca6f
Showing 1 changed file with 5 additions and 1 deletion.
diff --git a/avr-hal-generic/src/usart_spi.rs b/avr-hal-generic/src/usart_spi.rs
@@ -55,6 +55,9 @@ macro_rules! add_usart_spi {
                 fn raw_setup(&mut self, settings: &$crate::spi::Settings) {
                     use $crate::hal::spi;
 
+                    // UBRRn must be zero at the time the transmitter is enabled.
+                    self.[<ubrr $n>].write(|w| unsafe {w.bits(0)});
+
                     // We have to translate the character size register into the 2 bits which are the MSB/LSB and the phase
                     // 5 Bit Char = MSB and 1st
                     // 6 Bit Char = MSB and 2nd
@@ -80,13 +83,14 @@ macro_rules! add_usart_spi {
                         }
                     });
 
-                    // Enable receiver and transmitter, and also the rec interrupt.
+                    // Enable receiver and transmitter.
                     self.[<ucsr $n b>].write(|w| w
                         .[<txen $n>]().set_bit()
                         .[<rxen $n>]().set_bit()
                     );
 
                     // Set the clock divider for SPI clock.
+                    // This must be done after the transmitter is enabled.
                     self.[<ubrr $n>].write(|w| {
                         match settings.clock {
                             $crate::spi::SerialClockRate::OscfOver2 => w.bits(0),