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n64: improve PIF HLE emulation by reducing latency #1351

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merged 1 commit into from
Dec 17, 2023

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@rasky rasky commented Dec 17, 2023

When doing PIF HLE emulation, we run the HLE state machine just once per frame. This is OK in general, but there can be a few situations where this can cause PIF to miss one command from CPU. For instance, a ROM might send the PIF boot termination command (0x8) and then shortly after issue a SI DMA to identify controllers. If the two happen within the same frame, our HLE emulation would miss the boot termination command.

This commit updates the HLE state machine also after each write to PIF RAM.

When doing PIF HLE emulation, we run the HLE state machine just once per
frame. This is OK in general, but there can be a few situations where
this can cause PIF to miss one command from CPU. For instance, a ROM
might send the PIF boot termination command (0x8) and then shortly
after issue a SI DMA to identify controllers. If the two happen within
the same frame, our HLE emulation would miss the boot termination command.

This commit updates the HLE state machine also after each write to PIF
RAM.
@LukeUsher LukeUsher merged commit 18c84a8 into ares-emulator:master Dec 17, 2023
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