[#68174] Improve initialization of the examples

.github/scripts/tests/uartlite_sleep_after_1000_iters.patch

@@ -1,22 +1,15 @@
 diff --git a/src/Plugins/CoSimulationPlugin/IntegrationLibrary/src/renode_bus.cpp b/src/Plugins/CoSimulationPlugin/IntegrationLibrary/src/renode_bus.cpp
-index 2e425a734..5519bbce7 100644
 --- a/src/Plugins/CoSimulationPlugin/IntegrationLibrary/src/renode_bus.cpp
 +++ b/src/Plugins/CoSimulationPlugin/IntegrationLibrary/src/renode_bus.cpp
-@@ -179,6 +179,7 @@ void RenodeAgent::handleInterrupts(void)
-     }
- }
-
+@@ -198,8 +198,11 @@
 +#include <unistd.h>
- void RenodeAgent::simulate(int receiverPort, int senderPort, const char* address)
+ void RenodeAgent::simulate()
  {
-     renodeAgent = this;
-@@ -188,7 +189,9 @@ void RenodeAgent::simulate(int receiverPort, int senderPort, const char* address
      Protocol* result;
      reset();
 
 +    int iter = 0;
-     while(channel->getIsConnected()) {
+     while(communicationChannel->getIsConnected()) {
 +        if(++iter > 1000) sleep(600);
          result = receive();
          handleRequest(result);
-         delete result;

.github/scripts/tests/uartlite_wrong_ports.patch

@@ -1,13 +1,8 @@
 diff --git a/samples/uartlite/sim_main.cpp b/samples/uartlite/sim_main.cpp
-index f80e5b8..1e42fd3 100644
 --- a/samples/uartlite/sim_main.cpp
 +++ b/samples/uartlite/sim_main.cpp
-@@ -84,7 +84,7 @@ int main(int argc, char **argv, char **env) {
-     tfp->open("simx.vcd");
- #endif
-     RenodeAgent *uart = Init();
--    uart->simulate(atoi(argv[1]), atoi(argv[2]), address);
-+    uart->simulate(atoi(argv[1]) + 5, atoi(argv[2]) + 5, address);
-     top->final();
-     exit(0);
- }
+@@ -95,3 +95,3 @@ int main(int argc, char **argv, char **env) {
+     RenodeAgent *uart = initAgent();
+-    uart->connect(atoi(argv[1]), atoi(argv[2]), address);
++    uart->connect(atoi(argv[1]) + 5, atoi(argv[2]) + 5, address);
+     uart->simulate();

.github/scripts/tests/uartlite_wrong_second_port.patch

@@ -1,13 +1,8 @@
 diff --git a/samples/uartlite/sim_main.cpp b/samples/uartlite/sim_main.cpp
-index f80e5b8..f07a0ff 100644
 --- a/samples/uartlite/sim_main.cpp
 +++ b/samples/uartlite/sim_main.cpp
-@@ -84,7 +84,7 @@ int main(int argc, char **argv, char **env) {
-     tfp->open("simx.vcd");
- #endif
-     RenodeAgent *uart = Init();
--    uart->simulate(atoi(argv[1]), atoi(argv[2]), address);
-+    uart->simulate(atoi(argv[1]), atoi(argv[2]) + 5, address);
-     top->final();
-     exit(0);
- }
+@@ -95,3 +95,3 @@ int main(int argc, char **argv, char **env) {
+     RenodeAgent *uart = initAgent();
+-    uart->connect(atoi(argv[1]), atoi(argv[2]), address);
++    uart->connect(atoi(argv[1]), atoi(argv[2]) + 5, address);
+     uart->simulate();

samples/apb3uart/sim_main.cpp

@@ -1,5 +1,5 @@
 //
-// Copyright (c) 2010-2021 Antmicro
+// Copyright (c) 2010-2025 Antmicro
 //
 //  This file is licensed under the MIT License.
 //  Full license text is available in 'LICENSE' file.
@@ -34,15 +34,22 @@ void eval() {
     uart->eval();
 }
 
-RenodeAgent *Init() {
+UART* initAgent() {
     // These need static lifetime because we assign them to global pointers.
     // By having the initialization here we guarantee that any static initialization
     // from other compilation units (e. g. Verilator) is already done.
     static VerilatedContext context;
     static VApb3UartCtrl uart_ctrl_obj(&context);
-
     uart_ctrl = &uart_ctrl_obj;
 
+    const int murax_rxtx_reg = 0x0;
+    static UART uart_obj = UART(&uart_ctrl->io_uart_txd, &uart_ctrl->io_uart_rxd, prescaler, murax_rxtx_reg, &uart_ctrl->io_interrupt);
+
+    return &uart_obj;
+}
+
+void initBus(RenodeAgent *agent)
+{
     APB3* bus = new APB3();
 
     //=================================================
@@ -66,9 +73,13 @@ RenodeAgent *Init() {
     //=================================================
     // Init peripheral
     //=================================================
-    const int murax_rxtx_reg = 0x0;
-    static UART uart_obj = UART(bus, &uart_ctrl->io_uart_txd, &uart_ctrl->io_uart_rxd, prescaler, murax_rxtx_reg, &uart_ctrl->io_interrupt);
-    uart = &uart_obj;
+    agent->addBus(bus);
+}
+
+RenodeAgent* Init() {
+    uart = initAgent();
+    uart->connectNative();
+    initBus(uart);
     return uart;
 }
 
@@ -79,15 +90,18 @@ int main(int argc, char **argv, char **env) {
     }
     const char *address = argc < 4 ? "127.0.0.1" : argv[3];
 
-    Init();
     Verilated::commandArgs(argc, argv);
 #if VM_TRACE
     Verilated::traceEverOn(true);
     tfp = new VerilatedFstC;
     uart_ctrl->trace(tfp, 99);
     tfp->open("simx.fst");
 #endif
-    uart->simulate(atoi(argv[1]), atoi(argv[2]), address);
+
+    uart = initAgent();
+    uart->connect(atoi(argv[1]), atoi(argv[2]), address);
+    initBus(uart);
+    uart->simulate();
     uart_ctrl->final();
 
 #if VM_TRACE

samples/cpu_ibex/sim_main.cpp

@@ -24,26 +24,35 @@ void evaluateModel()
     ibex->evaluateModel();
 }
 
-RenodeAgent *Init()
+CpuAgent* initAgent()
 {
     Verilated::commandArgs(0, (const char **)nullptr);
+    CpuAgent* agent = new CpuAgent();
+    return agent;
+}
 
+void initBus(CpuAgent* agent)
+{
     WishboneInitiator<uint32_t, uint32_t> *instructionFetchBus = new WishboneInitiator<uint32_t, uint32_t>();
     WishboneInitiator<uint32_t, uint32_t> *loadStoreBus = new WishboneInitiator<uint32_t, uint32_t>();
 
-    agent = new CpuAgent(instructionFetchBus);
-    agent->addBus(loadStoreBus);
-
     ibex = new Ibex();
 
     ibex->setInstructionFetchBus(*instructionFetchBus);
     ibex->setLoadStoreBus(*loadStoreBus);
 
+    agent->addBus(instructionFetchBus);
+    agent->addBus(loadStoreBus);
     agent->addCPU(ibex);
 
     instructionFetchBus->evaluateModel = evaluateModel;
     loadStoreBus->evaluateModel = evaluateModel;
+}
 
+RenodeAgent* Init() {
+    agent = initAgent();
+    agent->connectNative();
+    initBus(agent);
     return agent;
 }
 
@@ -56,8 +65,10 @@ int main(int argc, char **argv, char **env)
     }
     const char *address = argc < 4 ? "127.0.0.1" : argv[3];
 
-    Init();
-    agent->simulate(atoi(argv[1]), atoi(argv[2]), address);
+    agent = initAgent();
+    agent->connect(atoi(argv[1]), atoi(argv[2]), address);
+    initBus(agent);
+    agent->simulate();
 
     return 0;
 }

samples/fastvdma/sim_main.cpp

@@ -1,5 +1,5 @@
 //
-// Copyright (c) 2010-2021 Antmicro
+// Copyright (c) 2010-2025 Antmicro
 //
 //  This file is licensed under the MIT License.
 //  Full license text is available in 'LICENSE' file.
@@ -19,7 +19,7 @@
 #include "src/buses/axilite.h"
 #include "src/renode_bus.h"
 
-RenodeAgent *fastvdma;
+RenodeAgent *fastvdma = new RenodeAgent;
 VDMATop *top = new VDMATop;
 VerilatedVcdC *tfp;
 vluint64_t main_time = 0;
@@ -34,7 +34,8 @@ void eval() {
     fastvdma->handleInterrupts();
 }
 
-RenodeAgent *Init() {
+void initAgent(RenodeAgent *agent)
+{
     AxiLite* bus = new AxiLite();
     AxiSlave* slaveBus = new AxiSlave(32, 32);
 
@@ -121,13 +122,16 @@ RenodeAgent *Init() {
     //=================================================
     // Init peripheral
     //=================================================
-    fastvdma = new RenodeAgent(bus);
-    fastvdma->addBus(slaveBus);
+    agent->addBus(bus);
+    agent->addBus(slaveBus);
 
-    fastvdma->registerInterrupt(&top->io_irq_writerDone, 0);
-    fastvdma->registerInterrupt(&top->io_irq_readerDone, 0);
+    agent->registerInterrupt(&top->io_irq_writerDone, 0);
+    agent->registerInterrupt(&top->io_irq_readerDone, 0);
+}
 
-    slaveBus->setAgent(fastvdma);
+RenodeAgent* Init() {
+    fastvdma->connectNative();
+    initAgent(fastvdma);
     return fastvdma;
 }
 
@@ -145,9 +149,12 @@ int main(int argc, char **argv, char **env) {
     top->trace(tfp, 99);
     tfp->open("simx.vcd");
 #endif
-    Init();
+
+    fastvdma->connect(atoi(argv[1]), atoi(argv[2]), address);
+    initAgent(fastvdma);
+    fastvdma->simulate();
     fastvdma->reset();
-    fastvdma->simulate(atoi(argv[1]), atoi(argv[2]), address);
+
     top->final();
     exit(0);
 }

samples/fpga_isp/sim_main.cpp

@@ -1,5 +1,5 @@
 //
-// Copyright (c) 2010-2022 Antmicro
+// Copyright (c) 2010-2025 Antmicro
 //
 //  This file is licensed under the MIT License.
 //  Full license text is available in 'LICENSE' file.
@@ -25,7 +25,7 @@
 #include "src/buses/axi.h"
 #include "src/renode_bus.h"
 
-RenodeAgent *isp;
+RenodeAgent *isp = new RenodeAgent;
 Vfpga_isp *top = new Vfpga_isp;
 vluint64_t main_time = 0;
 
@@ -43,7 +43,7 @@ void eval() {
     isp->handleInterrupts();
 }
 
-RenodeAgent *Init() {
+void initAgent(RenodeAgent *agent) {
     AxiSlave* slaveBus = new AxiSlave(32, 32);
     Axi* axi = new Axi(32, 32);
 
@@ -152,11 +152,8 @@ RenodeAgent *Init() {
     //=================================================
     // Init peripheral
     //=================================================
-    isp = new RenodeAgent(axi);
-    isp->addBus(slaveBus);
-
-    slaveBus->setAgent(isp);
-    axi->setAgent(isp);
+    agent->addBus(axi);
+    agent->addBus(slaveBus);
 
     isp->registerInterrupt(&top->irq_dmaIn, 0);
     isp->registerInterrupt(&top->irq_dmaOut, 1);
@@ -167,7 +164,11 @@ RenodeAgent *Init() {
     top->trace(tfp, 99);
     tfp->open(DEF_TRACE_FILEPATH);
 #endif
+}
 
+RenodeAgent* Init() {
+    isp->connectNative();
+    initAgent(isp);
     return isp;
 }
 
@@ -179,9 +180,10 @@ int main(int argc, char **argv, char **env) {
     const char *address = argc < 4 ? "127.0.0.1" : argv[3];
 
     Verilated::commandArgs(argc, argv);
-    Init();
+    isp->connect(atoi(argv[1]), atoi(argv[2]), address);
+    initAgent(isp);
     isp->reset();
-    isp->simulate(atoi(argv[1]), atoi(argv[2]), address);
+    isp->simulate();
     top->final();
     exit(0);
 }

samples/liteuart/sim_main.cpp

@@ -1,5 +1,5 @@
 //
-// Copyright (c) 2010-2021 Antmicro
+// Copyright (c) 2010-2025 Antmicro
 //
 //  This file is licensed under the MIT License.
 //  Full license text is available in 'LICENSE' file.
@@ -34,7 +34,13 @@ void eval() {
     uart->eval();
 }
 
-RenodeAgent *Init() {
+UART* initAgent() {
+    const int litex_rxtx_reg = 0x800;
+    return new UART(&top->serial_tx, &top->serial_rx, prescaler, litex_rxtx_reg, &top->irq_uart0);
+}
+
+void initBus(RenodeAgent *agent)
+{
     Wishbone* bus = new Wishbone();
 
     //=================================================
@@ -60,8 +66,13 @@ RenodeAgent *Init() {
     //=================================================
     // Init peripheral
     //=================================================
-    const int litex_rxtx_reg = 0x800;
-    uart = new UART(bus, &top->serial_tx, &top->serial_rx, prescaler, litex_rxtx_reg, &top->irq_uart0);
+    agent->addBus(bus);
+}
+
+RenodeAgent* Init() {
+    uart = initAgent();
+    uart->connectNative();
+    initBus(uart);
     return uart;
 }
 
@@ -79,8 +90,11 @@ int main(int argc, char **argv, char **env) {
     top->trace(tfp, 99);
     tfp->open("simx.fst");
 #endif
-    Init();
-    uart->simulate(atoi(argv[1]), atoi(argv[2]), address);
+    uart = initAgent();
+    uart->connect(atoi(argv[1]), atoi(argv[2]), address);
+    initBus(uart);
+    uart->simulate();
+
     top->final();
     exit(0);
 }