fixup! [#68174] Improve initialization of the examples

antmicro · Jan 22, 2025 · a508874 · a508874
1 parent 3d9bf3d
commit a508874
Show file tree

Hide file tree

Showing 8 changed files with 13 additions and 13 deletions.
diff --git a/samples/apb3uart/sim_main.cpp b/samples/apb3uart/sim_main.cpp
@@ -34,7 +34,7 @@ void eval() {
     uart->eval();
 }
 
-UART* initAgent() {
+UART *initAgent() {
     // These need static lifetime because we assign them to global pointers.
     // By having the initialization here we guarantee that any static initialization
     // from other compilation units (e. g. Verilator) is already done.
@@ -76,7 +76,7 @@ void initBus(RenodeAgent *agent)
     agent->addBus(bus);
 }
 
-RenodeAgent* Init() {
+RenodeAgent *Init() {
     uart = initAgent();
     uart->connectNative();
     initBus(uart);

diff --git a/samples/cpu_ibex/sim_main.cpp b/samples/cpu_ibex/sim_main.cpp
@@ -24,14 +24,14 @@ void evaluateModel()
     ibex->evaluateModel();
 }
 
-CpuAgent* initAgent()
+CpuAgent *initAgent()
 {
     Verilated::commandArgs(0, (const char **)nullptr);
     CpuAgent* agent = new CpuAgent();
     return agent;
 }
 
-void initBus(CpuAgent* agent)
+void initBus(CpuAgent *agent)
 {
     WishboneInitiator<uint32_t, uint32_t> *instructionFetchBus = new WishboneInitiator<uint32_t, uint32_t>();
     WishboneInitiator<uint32_t, uint32_t> *loadStoreBus = new WishboneInitiator<uint32_t, uint32_t>();
@@ -49,7 +49,7 @@ void initBus(CpuAgent* agent)
     loadStoreBus->evaluateModel = evaluateModel;
 }
 
-RenodeAgent* Init() {
+RenodeAgent *Init() {
     agent = initAgent();
     agent->connectNative();
     initBus(agent);

diff --git a/samples/fastvdma/sim_main.cpp b/samples/fastvdma/sim_main.cpp
@@ -129,7 +129,7 @@ void initAgent(RenodeAgent *agent)
     agent->registerInterrupt(&top->io_irq_readerDone, 0);
 }
 
-RenodeAgent* Init() {
+RenodeAgent *Init() {
     fastvdma->connectNative();
     initAgent(fastvdma);
     return fastvdma;

diff --git a/samples/fpga_isp/sim_main.cpp b/samples/fpga_isp/sim_main.cpp
@@ -166,7 +166,7 @@ void initAgent(RenodeAgent *agent) {
 #endif
 }
 
-RenodeAgent* Init() {
+RenodeAgent *Init() {
     isp->connectNative();
     initAgent(isp);
     return isp;

diff --git a/samples/liteuart/sim_main.cpp b/samples/liteuart/sim_main.cpp
@@ -34,7 +34,7 @@ void eval() {
     uart->eval();
 }
 
-UART* initAgent() {
+UART *initAgent() {
     const int litex_rxtx_reg = 0x800;
     return new UART(&top->serial_tx, &top->serial_rx, prescaler, litex_rxtx_reg, &top->irq_uart0);
 }
@@ -69,7 +69,7 @@ void initBus(RenodeAgent *agent)
     agent->addBus(bus);
 }
 
-RenodeAgent* Init() {
+RenodeAgent *Init() {
     uart = initAgent();
     uart->connectNative();
     initBus(uart);

diff --git a/samples/ram/sim_main.cpp b/samples/ram/sim_main.cpp
@@ -89,7 +89,7 @@ void initAgent(RenodeAgent *agent)
     agent->addBus(bus);
 }
 
-RenodeAgent* Init() {
+RenodeAgent *Init() {
     axi_ram->connectNative();
     initAgent(axi_ram);
     return axi_ram;

diff --git a/samples/uartlite/sim_main.cpp b/samples/uartlite/sim_main.cpp
@@ -33,7 +33,7 @@ void eval() {
 }
 
 RenodeAgent *initAgent() {
-    RenodeAgent * agent = new UART(&top->txd, &top->rxd, prescaler);
+    RenodeAgent *agent = new UART(&top->txd, &top->rxd, prescaler);
     AxiLite* bus = new AxiLite();
 
     //=================================================
@@ -71,7 +71,7 @@ RenodeAgent *initAgent() {
     return agent;
 }
 
-RenodeAgent* Init() {
+RenodeAgent *Init() {
     RenodeAgent *agent = initAgent();
     agent->connectNative();
     return agent;

diff --git a/samples/uartlite_extended/sim_main.cpp b/samples/uartlite_extended/sim_main.cpp
@@ -103,7 +103,7 @@ void initBus(RenodeAgent *agent) {
     agent->addBus(bus);
 }
 
-RenodeAgent* Init() {
+RenodeAgent *Init() {
     RenodeAgent *agent = initAgent();
     agent->connectNative();
     initBus(agent);