Updating submodules.

 * liteeth changed from f532a12 to 32d4af1
    * 32d4af1 - phy/__init__: import all phys. <Florent Kermarrec>
    * b2e1272 - phy: add tx/rx_clk_freq to phys (useful to add an add_ethernet method in LiteX and simplify timing constraints). <Florent Kermarrec>
    * 466223e - liteeth/gen: update copyrights <Florent Kermarrec>
    *   d6b5888 - Merge pull request #34 from Xiretza/generator-improvements <enjoy-digital>
    |\
    | * 7a44209 - Make memory/CSR regions customizable in config <Xiretza>
    | * ca9cbd1 - Move more options to config file <Xiretza>
    | * eea1086 - Use builder arguments in generator <Xiretza>
    | * b9fb1f0 - Remove leftover classes in generator <Xiretza>
    |/
    * 358bc23 - examples/.ymls: add separators <Florent Kermarrec>
    * ddcbc33 - test/test_gen: update <Florent Kermarrec>
    * fcadd60 - liteeth/gen: initial switch to YAML config file (similar to LiteDRAM/LitePCIe) <Florent Kermarrec>
    *   b029088 - Merge branch 'ximinity-generator-lattice' <Florent Kermarrec>
    |\
    | * 0954fa3 - Merge branch 'generator-lattice' of git://github.com/ximinity/liteeth into ximinity-generator-lattice <Florent Kermarrec>
    |/|
    | * ae10eea - gen: add lattice support <Stefan Schrijvers>
    * |   fcf7b24 - Merge pull request #33 from Xiretza/standalone-features <enjoy-digital>
    |\ \
    | * | 5767dfc - Honour --output-dir argument in generator <Xiretza>
    | * | 153c160 - Prioritise overridden interrupts and memory regions <Xiretza>
    | * | ec9bc57 - Fix MII tx_en signal width in standalone generator <Xiretza>
    | * | 42a7b6c - Allow little-endian interface for standalone design <Xiretza>
    | * | a696ccd - Expose interrupt pin for standalone design <Xiretza>
    |/ /
    * | 208bc09 - liteeth/gen: update <Florent Kermarrec>
    * | ddd0431 - examples: use integrated sram instead of external one. (Also fix regression with new SoC that no longer support address decoders passed to add_wb_slave) <Florent Kermarrec>
    |/
    * 081bf46 - mac/sram: simplify code and improve SRAM read speed using async_read on Memory. <Florent Kermarrec>
    * bf4a11a - mac/sram: simplify counter (use NextValue in FSM) <Florent Kermarrec>
    * 721238b - mac/sram: cosmetic changes <Florent Kermarrec>

 * litepcie changed from 17beae4 to b544659
    * b544659 - frontend/dma/LitePCIeDMAReader: compute and use pending words to decide if the request should be sent. <Florent Kermarrec>
    * 43035ea - phy: add Ultrascale PHY skeleton. <Florent Kermarrec>
    * b3c07d3 - core/endpoint: add support for separate request/completion channels on the PHY. <Florent Kermarrec>
    * b4c013c - phy/s7pciephy: fix typo. <Florent Kermarrec>
    * 5962934 - core/msi: add CSRs descriptions. <Florent Kermarrec>
    * 6066f87 - frotend/dma: improve CSR descriptions and fix typos. <Florent Kermarrec>
    * 2c68b46 - phy/s7pciephy: improve CSR names and add description. <Florent Kermarrec>

 * litex changed from 02bfda5e to 536ae0e6
    *   536ae0e6 - Merge pull request #425 from esden/csr-cod-split-reg <Sean Cross>
    |\
    | * 57576fa8 - Add bit more logic to decide when to switch to multilane CSR documentation. <Piotr Esden-Tempski>
    | * dda7a8c5 - Split CSR documentation diagrams with more than 8 bits into multiple lanes. <Piotr Esden-Tempski>
    |/
    *   c0f067c3 - Merge pull request #427 from enjoy-digital/s7mmcm_fractional_divide <enjoy-digital>
    |\
    | * aec1bfbe - cores/clock: simplify Fractional Divide support on S7MMCM. <Florent Kermarrec>
    |/
    *   f34593a1 - Merge pull request #421 from betrusted-io/clk0_fractional <enjoy-digital>
    |\
    | * 5b92bf2d - add fractional division options to clk0 config on PLL <bunnie>
    * | eb9f54b2 - test: add initial (minimal) test for clock abstraction modules. <Florent Kermarrec>
    * | c304c4db - targets/icebreaker: add description of the board, link to crowdsupply campagin and to the more complete example. <Florent Kermarrec>
    * |   b5bddc23 - Merge pull request #426 from esden/update-wavedrom <Sean Cross>
    |\ \
    | * | d063acb7 - Updating the vendored wavedrom js files. <Piotr Esden-Tempski>
    |/ /
    * | a27385a7 - soc/intergration: rename mr_memory_x parameter to memory_x. <Florent Kermarrec>
    * |   d5da9e0d - Merge pull request #424 from esden/generate-memory-x <enjoy-digital>
    |\ \
    | * | 4d022632 - Add --mr-memory-x parameter to generate memory regions memory.x file. <Piotr Esden-Tempski>
    |/ /
    * |   e9f0ff68 - Merge branch 'master' of http://github.com/enjoy-digital/litex <Florent Kermarrec>
    |\ \
    | * \   01b69693 - Merge pull request #422 from xobs/core-doc-fixes <Sean Cross>
    | |\ \
    | | * | a2f61b4e - soc/cores/spi_opi: documentation fixes <Sean Cross>
    | | * | d2f6139d - soc/cores/i2s: fix rst parsing errors <Sean Cross>
    | | |/
    | * |   4ccf62af - Merge pull request #423 from gsomlo/gls-ethmac-fixes <enjoy-digital>
    | |\ \
    | | * | a9040348 - integration/soc: add_ethernet: honor self.map["ethmac"], if present <Gabriel Somlo>
    * | | | 979f98ea - software: revert LTO changes (Disable it). <Florent Kermarrec>
    |/ / /
    * | | bb8905fa - cores/gpio: add CSR descriptions. <Florent Kermarrec>
    * | | 4dabc5a6 - cores/icap: add CSR descriptions. <Florent Kermarrec>
    * | | 77132a48 - cores/spi: add CSR descriptions. <Florent Kermarrec>
    * | | 6d861c6e - cores/pwm: add CSR descriptions. <Florent Kermarrec>
    * | | cbc1f594 - cores/xadc: add CSR descriptions. <Florent Kermarrec>
    |/ /
    * | 846a2720 - targets/kcu105: move cd_pll4x. <Florent Kermarrec>
    * | c97fabb2 - targets/kcu105: simplify CRG using USIDELAYCTRL. <Florent Kermarrec>
    * | 3c0b97ee - cores/clock/USIDELAYCTRL: use separate reset/ready counters and set cd_sys.rst internally. <Florent Kermarrec>
    * | bcbf558b - bios: add more Ultrascale SDRAM debug with sdram_cdly command to set clk/cmd delay. <Florent Kermarrec>
    * |   c4ce6da6 - Merge pull request #419 from gsomlo/gls-ultra-sdram-fixup <enjoy-digital>
    |\ \
    | * | 4d15e1f7 - software/bios: fixup for Ultrascale SDRAM debug <Gabriel Somlo>
    * | | b5090687 - cores/clock: add logging to visualize clkin/clkouts and computed config. <Florent Kermarrec>
    * | | 04b8a912 - integration/soc: add FPGA device and System clock to logs. <Florent Kermarrec>
    * | | 02cba41d - targets/icebreaker: create CRG after SoC. <Florent Kermarrec>
    |/ /
    * | ba2f31d4 - integration/soc: set use_rom when cpu_reset_address is defined in a rom region. <Florent Kermarrec>
    * | 8808c884 - boards/platforms/icebreaker: cleanup a bit. <Florent Kermarrec>
    * | 4656b1b2 - software/common: fix LTO checks. <Florent Kermarrec>
    * | 2a91dead - soc/cores/clock/iCE40PLL: add SB_PLL40_PAD support. <Florent Kermarrec>
    * | 38d7f8a6 - build/lattice/icestorm: add timingstrict parameter and default to False. (similar behavior than others backends) <Florent Kermarrec>
    * | 1e9aa643 - targets/icebreaker: simplify, use standard VexRiscv, add iCE40PLL and run BIOS from SPI Flash. <Florent Kermarrec>
    * | 197bdcb0 - lattice/icestorm: enable DSP inference with Yosys and avoid setting SPI Flash in deep sleep mode after configuration which prevent running ROM CPU code from SPI Flash. <Florent Kermarrec>
    * | 37869e38 - boards: add initial icebreaker platform/target from litex-boards. <Florent Kermarrec>
    * | 72af1b39 - software/bios: add Ultrascale SDRAM debug functions. <Florent Kermarrec>
    * | 6480d180 - boards/platforms/kcu105: avoid unnecessary {{}} on INTERNAL_VREF. <Florent Kermarrec>
    * | b02c2339 - integration/soc/SoCRegion: add size_pow2 and use this internally for checks since decoder is using rounded size to next power or 2. <Florent Kermarrec>
    |/
    * e801dc02 - soc: allow creating SoC without BIOS. <Florent Kermarrec>
    *   5ded1447 - Merge pull request #416 from enjoy-digital/csr_svd <enjoy-digital>
    |\
    | * ecca3d80 - integration/builder: rename software methods to _prepare_rom_software/_generate_rom_software/_initialize_rom_software. <Florent Kermarrec>
    | * 69ffafd8 - integration/builder: generate csr maps before compiling software. <Florent Kermarrec>
    | * e2dab063 - Add SVD export capability to Builder (csr_svd parameter) and targets (--csr-svd argument) and fix svd regression. <Florent Kermarrec>
    |/
    * e124aed9 - software/common.mak: fix LTO refactoring issue. <Florent Kermarrec>
    *   8bfb845f - Merge pull request #412 from antmicro/fix-copyrights <enjoy-digital>
    |\
    | * da580e31 - Fix copyrights <Karol Gugala>
    |/
    *   361b6a06 - Merge pull request #408 from gsomlo/gls-fix-nexys-sdcard <enjoy-digital>
    |\
    | * 020bef41 - targets/nexys4ddr: fix sdcard clocker initialization <Gabriel Somlo>
    |/
    *   9249fc90 - Merge pull request #410 from antmicro/netv2-edid <enjoy-digital>
    |\
    | * 72f63243 - platform/netv2: add proper I2C pins for HDMI IN0 <Piotr Binkowski>
    * | ad11ff39 - targets/ecp5: make sure all BaseSoC/EthernetSoc default to trellis. <Florent Kermarrec>
    * | 37701950 - bios/sdcard: update sdclk_mmcm_write with LiteSDCard clocker changes. <Florent Kermarrec>
    * | 4c83c975 - doc: align to improve readability. <Florent Kermarrec>
    * | 4f935714 - soc/doc: remove soc.get_csr_regions support. <Florent Kermarrec>
    * | 6893222c - bios/main: rename flushl2 command to flush_l2_cache, add flush_cpu_dcache command and expose them in help. <Florent Kermarrec>
    * | d2accbb1 - README: update quick start guide and add instructions for windows. <Florent Kermarrec>
    * | fc9b3975 - README: update - improve presentation - add link to #litex freenode channel. - add example of complex SoC. - make it directly usable on Wiki. - only keep one quick start guide. - add community paragraph and link to Litex-Hub. <Florent Kermarrec>
    * | 68f56542 - doc: remove partial doc imported from litex-buildenv-wiki: we'll create a LiteX wiki and doc. <Florent Kermarrec>
    * | 0b923aa4 - build: assume vendor tools are in the PATH and remove automatic sourcing, source and toolchain_path parameters. <Florent Kermarrec>
    * | 1d7c6943 - software/common: add LTO enable flag and cleanup. <Florent Kermarrec>
    * | b29f443f - litex_sim: fix with_uart parameter. <Florent Kermarrec>
    |/
    * 98e41e2e - targets/nexys4ddr: add default kwargs parameters. <Florent Kermarrec>
    *   598ad692 - Merge branch 'master' of https://github.com/enjoy-digital/litex <Florent Kermarrec>
    |\
    | *   ddb264f3 - Merge pull request #405 from sajattack/sifive-triple <enjoy-digital>
    | |\
    | | * 68c013d1 - add riscv-sifive-elf triple <Paul Sajna>
    * | | a67e19c6 - integration/soc_core: change disable parameters to no-xxyy. <Florent Kermarrec>
    * | | 156a85b1 - integration/soc: add auto_int type and use it on all int parameters. <Florent Kermarrec>
    * | | 7e96c911 - targets/nexys4ddr: use SoCCore and add_sdram to avoid use of specific SoCSDRAM. <Florent Kermarrec>
    * | | cb0371b3 - integration/soc: add ethphy CSR in target. <Florent Kermarrec>
    |/ /
    * | f27225c2 - targets/nexys4ddr: use soc.add_ethernet method. <Florent Kermarrec>
    * | 9735bd5b - integration/soc: add add_ethernet method. <Florent Kermarrec>
    * | 1c74143a - integration/soc: mode litedram imports to add_sdram, remove some separators. <Florent Kermarrec>
    |/
    * 54fb3a61 - test/test_targets: use uart-name=stub. <Florent Kermarrec>
    * 59e99bfb - soc/uart: add configurable UART FIFO depth. <Florent Kermarrec>
    * 9199306a - cores/uart: cleanup <Florent Kermarrec>
    * ea856333 - soc/cores/uart/UARTCrossover: reduce fifo_depth to 1. <Florent Kermarrec>
    * 12a75286 - interconnect/stream/SyncFIFO: allow depth down to 0. <Florent Kermarrec>
    * 9e31bf35 - interconnect/axi: remove Record inheritance on AXIInterface/AXILiteInterface. <Florent Kermarrec>
    * 1e0e96f9 - interconnect/axi: add AXI Stream definition and get_ios/connect_to_pads methods. <Florent Kermarrec>
    * 6be7e9c3 - interconnect/axi: set default data_width/address_width to 32-bit. <Florent Kermarrec>
    * 8e1d5286 - targets: default to trellis toolchain on all ECP5 targets (now able to build all supported targets). <Florent Kermarrec>
    * a7c5dd5d - cores/gpio: use separate TSTriple for each bit. <Florent Kermarrec>
    * 400492e2 - lattice/yosys: don't use quiet operation since logs are useful and for consistency with others build backends. <Florent Kermarrec>
    * c4fd6a7f - targets/kc705: use DDRPHY_CMD_DELAY to center write leveling. <Florent Kermarrec>
    * 78a32235 - software/bios/sdram: allow setting CLK/CMD delay from user design and configure it before write/read leveling. <Florent Kermarrec>
    * eab5161d - boards: keep in sync with LiteX-boards <Florent Kermarrec>
    * 935e4eff - interconnect/axi: remove mode on AXIInterface (not used and breaking LiteDRAM tests) <Florent Kermarrec>
    * d324c54e - integration/soc: -x on soc.py <Florent Kermarrec>
    * ee27a9e5 - soc/cores/bitbang: fix missing self.comb on miso. <Florent Kermarrec>
    *   a2d69869 - Merge pull request #402 from antmicro/litex-gen-fix-uart-pins <enjoy-digital>
    |\
    | * 75b000a3 - tools: litex_gen: fix missing UART pins <Jan Kowalewski>
    * | e2aebb42 - software: disable LTO with LM32 (not supported by old GCC versions easily available). <Florent Kermarrec>
    * |   9e70fcf8 - Merge pull request #401 from antmicro/enable-lto <enjoy-digital>
    |\ \
    | |/
    |/|
    | * 718a65c3 - software: enable link time optimization (LTO) <Tim 'mithro' Ansell>
    |/
    *   9521f2ff - Merge pull request #400 from Xiretza/ecp5-pll-freqfix <enjoy-digital>
    |\
    | * 7a87d4e2 - Fix ECP5PLL VCO frequency range <Xiretza>
    |/
    * 0c7e0bf0 - integration/soc: improve presentation of SoCLocHandler's locations. <Florent Kermarrec>
    * 0042a028 - interconnect/axi: remove bus_name on connect_to_pads <Florent Kermarrec>
    * 5aba1fe8 - tools/litex_gen: add bus parameter and AXI (Lite) support. <Florent Kermarrec>
    * a3584147 - litex_gen/axi: simplify the way the bus is exposed as ios and connected to pads. <Florent Kermarrec>
    * d86db6f1 - litex_gen/wishbone: simplify the way the bus is exposed as ios and connected to pads. <Florent Kermarrec>
    * 18c57a64 - tools: rename litex_extract to litex_gen (use similar name than litedram/liteeth generators) and cleanup/simplify. <Florent Kermarrec>
    *   0083e097 - Merge pull request #396 from antmicro/external-wb <enjoy-digital>
    |\
    | * 9e2aede8 - tools: add script for extracting wishbone cores <Piotr Binkowski>
    | * 79a14001 - axi: add to_pads method <Karol Gugala>
    | * e0bcb57d - wishbone: add extracting module signals to the top <Jan Kowalewski>
    * |   017c91a4 - Merge pull request #397 from gsomlo/gls-csr-volatile <enjoy-digital>
    |\ \
    | |/
    |/|
    | * 173117ad - Add 'volatile' qualifier to new CSR accessors <Gabriel Somlo>
    |/
    * 485934ed - doc/socdoc: fix example <Florent Kermarrec>
    * 53ee9a5e - cpu/blackparrot: first cleanup pass <Florent Kermarrec>
    * f3829cf0 - integration/soc: set base_address on LiteDRAMWishbone2Native, fix addressing with >= 1GB SDRAMs. <Florent Kermarrec>
    * 3a6f97ff - build/sim: add Verilator FST tracing support. <Florent Kermarrec>
    *   8a715f3b - Merge pull request #390 from gsomlo/gls-add-sdcard <enjoy-digital>
    |\
    | * 516cf405 - targets/nexys4ddr: add optional sdcard support <Gabriel Somlo>
    | * d4d2b7f7 - bios: add litesdcard test routines to boot menu <Gabriel Somlo>
    | * 7a2e33b8 - targets/nexys4ddr: add ethernet via method instead of inheritance <Gabriel Somlo>
    |/
    * 774a55a2 - soc_core: fix missing init on main_ram <Florent Kermarrec>
    *   5d580ca4 - Merge pull request #389 from antmicro/linux_flash_offsets <enjoy-digital>
    |\
    | * 659c244a - bios/boot: allow to customize flash offsets of Linux images <Mateusz Holenko>
    * | 00895518 - cores/cpu: use standard+debug variant when only debug is specified. <Florent Kermarrec>
    |/
    * ae45be47 - soc/cores/clock: add reset_cycles parameter to S7IDELAYCTRL/USIDELAYCTRL <Florent Kermarrec>
    * 9baa3ad5 - soc/csr_bus: fix aligned_paging computation (should be done with SoC's Bus data width not bus.alignment) <Florent Kermarrec>
    * 854e7cc9 - integration/soc: improve Region logger <Florent Kermarrec>
    * 9cb8f68e - bios/boot: update and fix flashboot, improve verbosity <Florent Kermarrec>
    * 6ed0f445 - soc: increase supporteds address_width/paging <Florent Kermarrec>
    * 5b3808cb - soc_core: expose CSR paging <Florent Kermarrec>
    * 0497f3ca - soc/csr_bus: improve CSR paging genericity <Florent Kermarrec>
    * 351896bf - tools/litex_sim: use new sdram verbosity parameter <Florent Kermarrec>
    * 67e8a042 - integration/soc: add configurable CSR Paging <Florent Kermarrec>
    * 65764701 - soc_core: add back identifier <Florent Kermarrec>
    *   8f6114d0 - Merge pull request #387 from BracketMaster/master <enjoy-digital>
    |\
    | * 3da204ed - update to work with mac <Yehowshua Immanuel>
    * | 3574b909 - tools/litex_sim: specify default local/remote-ip addresses. <Florent Kermarrec>
    * | aebaea77 - tools/litex_sim: add ethernet local/remote-ip arguments. <Florent Kermarrec>
    |/
    * 18a9d4ff - interconnect/stream: cleanup imports/idents <Florent Kermarrec>
    *   57fb3720 - Merge pull request #386 from antmicro/sdram-timing-checker <enjoy-digital>
    |\
    | * eff85a99 - tools/litex_sim: add cli options to control SDRAM timing checker <Piotr Binkowski>
    |/
    * e4712ff7 - soc_core: fix cpu_variant renaming regression <Florent Kermarrec>
    * a2f1683b - doc: rename lxsocdoc -> socdoc and update readme <Sean Cross>
    * baa29f1b - doc: fix regression with new irq manager <Sean Cross>
    * 1620f9c5 - soc/CSR: show alignment in report and add info when updating. <Florent Kermarrec>
    * 5b34f4cd - soc/add_cpu: use cpu.data_width as CSR alignment, fix regression on Rocket <Florent Kermarrec>
    * 2f69f607 - integration/soc: fix refactoring issues <Florent Kermarrec>
    * 1d6ce66b - soc/integration/builder: update copyright, align arguments <Florent Kermarrec>
    *   98ae91ad - Merge pull request #383 from Xiretza/builder-directories <enjoy-digital>
    |\
    | * b5654579 - Unify output directory handling in builder <Xiretza>
    |/
    *   4a15c3e2 - Merge pull request #382 from enjoy-digital/new_soc <enjoy-digital>
    |\
    | * e9c665a5 - soc_core/soc_sdram: add disclaimer <Florent Kermarrec>
    | * 5558865c - soc_core: provide full retro-compatibily when add_wb_slave is called before add_memory_region <Florent Kermarrec>
    | * 1b5caf56 - soc: fix busword typo <Florent Kermarrec>
    | * 8b5cc345 - targets/EthernetSoC: be sure memory region is added before adding Wishbone Slave (required by new SoC) <Florent Kermarrec>
    | *   240a55ba - Merge branch 'master' into new_soc <enjoy-digital>
    | |\
    | |/
    |/|
    * | d5ad1d56 - soc/integration: move mem_decoder to soc_core <Florent Kermarrec>
    * | 0a737cb6 - soc/integration/common: simplify get_version <Florent Kermarrec>
    * | 4d761e1a - cores/cpu: remove separators on io_regions (requires python 3.6) <Florent Kermarrec>
    * |   7c57a33b - Merge pull request #380 from Xiretza/cpunone-all-io <enjoy-digital>
    |\ \
    | * | e301df7f - Allow all memory regions to be used as IO with CPUNone <Xiretza>
    |/ /
    * | 16d1972b - integration/common: fix mem_decoder (shadow base has been deprecated) <Florent Kermarrec>
    * | 7ee9ce38 - .gitmodules/black-parrot: switch to https://github.com/enjoy-digital/black-parrot (without the submodules) <Florent Kermarrec>
    * |   1dced818 - Merge pull request #278 from scanakci/blackparrot_litex <enjoy-digital>
    |\ \
    | * | d15c911c - BlackParrot initial commit w/ Litex BIOS simulation including LiteDRAM w/ Litex BIOS working on FPGA excluding LiteDRAM <sadullah>
    * | | 1d70ef69 - soc/cores/spi_opi: cleanup, rename to S7SPIOPI (since 7-Series specific for now) <Florent Kermarrec>
    * | | 62f3537d - soc/cores: rename spiopi to spi_opi <Florent Kermarrec>
    * | | f58e8188 - soc/cores/i2s: cleanup pass, rename to S7I2SSlave (since 7-Series specific for now), rename fifodepth to fifo_depth for consistency with others cores. <Florent Kermarrec>
    * | |   c2c80b5d - Merge pull request #378 from betrusted-io/merge_ip <enjoy-digital>
    |\ \ \
    | * | | 98e46c27 - reduce indents <bunnie>
    | * | | d2b394a9 - update doc comments on events for i2s <bunnie>
    | * | | 416afd31 - add doc comment for event <bunnie>
    | * | | 33d9e45a - fix formatting on spiopi <bunnie>
    | * | | cc6ed667 - Request to merge I2S and SPIOPI cores <bunnie>
    | | | * 399b65fa - soc/add_uart: fix bridge <Florent Kermarrec>
    | | | * 160c55d1 - soc_core/soc_sdram: remove disclaimer (we'll add it later when designs will be adapted) <Florent Kermarrec>
    | | | * b2c66b1e - soc: avoid double definition of main_ram <Florent Kermarrec>
    | | | * 5f994608 - soc: improve log colors on error reporting <Florent Kermarrec>
    | | | * b22d2ca0 - soc: add linker regions management <Florent Kermarrec>
    | | | * abc31a92 - soc: improve log presentation/colors <Florent Kermarrec>
    | | | * 91e2797b - soc: fix cpu_reset_address <Florent Kermarrec>
    | | | * 0d7430fc - tools/litex_sim_new: remove <Florent Kermarrec>
    | | | * 21d38701 - soc: fix build_time format <Florent Kermarrec>
    | | | * b43d830f - soc/add_sdram: simplify L2 Cache, use FullMemoryWE on L2 Cache by default (seems better on all devices) <Florent Kermarrec>
    | | | * ea8e745a - soc_core/common: move old mem_decoder to soc_core, simplify get_version <Florent Kermarrec>
    | | | * 5e11e839 - tools/litex_sim_new: switch to dynamically allocated ethmac origin <Florent Kermarrec>
    | | | * dd0c71d7 - soc/SoCRegion/Decoder: pass bus to decoder and remove mask on origin <Florent Kermarrec>
    | | | * e8e4537e - soc/add_sdram: avoid L2 cache when l2_cache_size == 0. <Florent Kermarrec>
    | | | * dcbdb732 - soc: remove unneeded \n <Florent Kermarrec>
    | | | * 0f1811fb - tools/litex_sim_new: use new bus/csr/irq methods <Florent Kermarrec>
    | | | * d320be8e - soc: use io_regions for alloc_region <Florent Kermarrec>
    | | | * 9ac09ddd - tools: add litex_sim_new based on SoCCore and using add_sdram method <Florent Kermarrec>
    | | | * cbcd953d - soc_core: use add_rom <Florent Kermarrec>
    | | | * 487ac3da - soc/add_cpu: simplify CPUNone integration <Florent Kermarrec>
    | | | * f7d4648c - soc/SoCBusHandler: add add_adapter method and use it to convert Master/Slave before connecting to the Bus <Florent Kermarrec>
    | | | * 379d47a8 - soc/add_sdram: add sdram csr <Florent Kermarrec>
    | | | * 3921b634 - soc/add_sdram: fix rocket, shorten comments <Florent Kermarrec>
    | | | * 14b627b4 - soc/add_sdram: improve API <Florent Kermarrec>
    | | | * 1faefdc0 - soc: add LiteXSoC class and mode add_identifier/uart/sdram to it <Florent Kermarrec>
    | | | * 11dbe190 - soc_core/sdram: cleanup, add disclaimer <Florent Kermarrec>
    | | | * 5eb88cd9 - soc: add add_sdram <Florent Kermarrec>
    | | | * 39011593 - soc: add csr_regions, update copyright <Florent Kermarrec>
    | | | * d2b06951 - soc: add cpu rom/sram check <Florent Kermarrec>
    | | | * de100fdd - soc: add SOCIORegion and manage it <Florent Kermarrec>
    | | | * 6b8c425f - soc: reorder main components/peripherals <Florent Kermarrec>
    | | | * 84b5df78 - soc: add add_cpu method <Florent Kermarrec>
    | | | * b676a559 - soc: fix unit-tests <Florent Kermarrec>
    | | | * 0a588390 - soc: integrate constants/build <Florent Kermarrec>
    | | | * 014d5a56 - soc: show sorted regions (by origin) / locs <Florent Kermarrec>
    | | | * c69b6b7c - soc: simplify color theme <Florent Kermarrec>
    | | | * 3cb90297 - soc: add add_uart method <Florent Kermarrec>
    | | | * e5cacb8b - soc_core: cleanup imports <Florent Kermarrec>
    | | | * 33d498b8 - soc_core: get_csr_address no longer used <Florent Kermarrec>
    | | | * 1feff1d7 - soc: integrate CSR master/interconnect/collection and IRQ collection <Florent Kermarrec>
    | | | * 3ba7c29e - soc: add add_constant/add_config methods <Florent Kermarrec>
    | | | * 29bbe4c0 - soc: add add_csr_bridge method <Florent Kermarrec>
    | | | * b84c291c - soc: add add_controller/add_identifier/add_timer methods <Florent Kermarrec>
    | | | * 9445c33e - soc: add add_ram/add_rom methods <Florent Kermarrec>
    | | | * e5a8ac1d - soc: add automatic bus data width convertion to add_master/add_slave <Florent Kermarrec>
    | | | * 8f67f115 - soc/soc_core: cleanup, remove some unused attributes <Florent Kermarrec>
    | | | * 2c6e5066 - soc: move SoCController from soc_core to soc <Florent Kermarrec>
    | | | * 848fa20d - soc: create SoCLocHandler and use it to simplify SoCCSRHandler and SoCIRQHandler <Florent Kermarrec>
    | | | * 39458c92 - soc: add use_loc_if_exists on SoCIRQ.add to use current location is already defined <Florent Kermarrec>
    | | | * 1eff0799 - soc: add use_loc_if_exists on SoCCSR.add to use current location is already defined <Florent Kermarrec>
    | | | * 8bc42067 - soc/integration: initial adaptation to new SoC class <Florent Kermarrec>
    | | | * 6baa07a6 - soc/integration: add new soc class prorotype with SoCRegion/SoCBus/SoCCSR/SoCIRQ/SoC <Florent Kermarrec>
    | |_|/
    |/| |
    * | | 9b11e919 - cpu/vexriscv: update submodule <Florent Kermarrec>
    |/ /
    * | ae085782 - doc: add lxsocdoc.md (README from lxsocdoc repository) <Sean Cross>
    * |   5ff02e23 - Merge pull request #375 from xobs/add-lxsocdoc <enjoy-digital>
    |\ \
    | * | 58598d4f - integration: svd: move svd generation to `export` <Sean Cross>
    | * | 73ed7e56 - soc: doc: use sphinx toctree as it was intended <Sean Cross>
    | * | 7c3bc0b0 - litex-doc: initial merge of lxsocdoc <Sean Cross>
    * | | 1944d8d9 - bios/main: add LiteX tagline <Florent Kermarrec>
    * | |   40cddca9 - Merge pull request #376 from antmicro/build-sim-do-not-override-C-LD-FLAGS <enjoy-digital>
    |\ \ \
    | |/ /
    |/| |
    | * | 90fe5850 - build/sim: allow to use environment's {C,LD}FLAGS <Mariusz Glebocki>
    |/ /
    * |   bd6fd3da - Merge pull request #373 from antmicro/l2-reverse <enjoy-digital>
    |\ \
    | * | f3b068e2 - tools/litex_sim: use l2_reverse flag <Piotr Binkowski>
    |/ /
    * | 3350d33f - wishbone/Cache: add reverse parameter <Florent Kermarrec>
    * | eff9caee - soc_sdram: add l2_reverse parameter <Florent Kermarrec>
    * |   6e5b47f4 - Merge pull request #370 from Disasm/fixes <enjoy-digital>
    |\ \
    | * | de88ed28 - Fix argument descriptions <Vadim Kaushan>
    | * | eb49ec21 - Pass --csr-json to the Builder <Vadim Kaushan>
    |/ /
    * | b69f2993 - soc_core: add UART bridge support (simplify having to do it externally) <Florent Kermarrec>
    * | 7a6c04db - build/altera/quartus: fix fmt_r typo <Florent Kermarrec>
    * | c6b9676d - cpu/minerva: update (use new nMigen API) <Florent Kermarrec>
    * | 9d289472 - inteconnect/stream: use PipeValid implementation for Buffer <Florent Kermarrec>
    * | 1c88c0f8 - inteconnect/stream: cleanup <Florent Kermarrec>
    * |   cafd9c35 - Merge pull request #366 from gsomlo/gls-csr-followup <enjoy-digital>
    |\ \
    | * | ff2775c2 - software, integration/export: (re-)expose CSR subregister accessors <Gabriel Somlo>
    * | | f3f9808d - interconnect/stream: add PipeValid and PipeWait to cut timing paths. <Florent Kermarrec>
    * | | b22ad1ac - build/xilinx/vivado: improve readability of generated tcl/xdc files <Florent Kermarrec>
    |/ /
    * | 7bc34a9b - integration/soc_core: revert integrate_sram_size default value (cause issues when using External SPRAM). <Florent Kermarrec>
    * |   b4b56db4 - Merge pull request #363 from antmicro/litex-sim-ddr4 <enjoy-digital>
    |\ \
    | * | c02dd5e8 - tools/litex_sim: add ddr4 PhySettings <Piotr Binkowski>
    |/ /
    * | 0820adbd - tools/litex_sim: add --sdram-init parameter <Florent Kermarrec>
    * | 01ae10b8 - software/bios: revert M-Labs MiSoC copyright. <Florent Kermarrec>
    * | ea5ef8c1 - README: update copyright year and make sure LICENSE/README both mention MiSoC <Florent Kermarrec>
    * | 95cfa6a8 - platforms/netv2: add pcie pins <Florent Kermarrec>
    * |   f9bc98ed - Merge pull request #359 from gregdavill/bios_ddr3_ecp5 <enjoy-digital>
    |\ \
    | * | 1f439062 - soc/software/bios/sdram: ECP5 move strobe dly_sel <Greg Davill>
    | * | f84f57d6 - soc/software/bios/sdram: On ECP5 strobe dly_sel after read leveling <Greg Davill>
    |/ /
    * | 52765488 - tools/litex_sim: update copyrights and cosmetic changes <Florent Kermarrec>
    * |   b280bb2f - Merge pull request #358 from antmicro/litex_sim_ddr <enjoy-digital>
    |\ \
    | * | 9aa97c2e - tools/litex_sim: add support for other sdram types (DDR, LPDDR, DDR2, DDR3) <Piotr Binkowski>
    * | | 19ef19ce - cores/clock/create_clkout: rename clk_ce to ce, improve error reporting <Florent Kermarrec>
    * | |   7e088360 - Merge pull request #357 from betrusted-io/add_clk_ce <enjoy-digital>
    |\ \ \
    | |/ /
    |/| |
    | * | 1f7549b4 - add BUFIO to clockgen buffer options <bunnie>
    | * | b3f9aa11 - add option for BUFGCE to the clock generator buffer types <bunnie>
    * | | cbc081c4 - tools/litex_sim: review/cleanup sdram-module/sdram-data-width features. <Florent Kermarrec>
    * | |   b35ea459 - Merge pull request #354 from antmicro/litex_sim_ddr <enjoy-digital>
    |\ \ \
    | * | | 674cfcde - tools/litex_sim: specify dram chip and data width via commandline <Piotr Binkowski>
    * | | |   b23f13d9 - Merge pull request #351 from antmicro/fix_sram_size_argument <enjoy-digital>
    |\ \ \ \
    | |/ / /
    |/| | |
    | * | | 7a05353a - soc_core: rename integrated_sram_size argument <Mateusz Holenko>
    | * | | c4bb4169 - soc_core: fix integrated_sram_size argument type <Mateusz Holenko>
    * | | | 5845df76 - build/xilinx/vivado: add pre_placement/pre_routing commands <Florent Kermarrec>
    * | | | 13880882 - cores/icap: add add_timing_constraints method <Florent Kermarrec>
    * | | | 2074a86e - cores/dna: cleanup and add add_timing_constraints method <Florent Kermarrec>
    |/ / /
    * | | d39dc8cf - tools/litex_sim: cleanup/simplify <Florent Kermarrec>
    * | | a0d95766 - build/sim: add -Wl,--no-as-needed to LDFLAGS for Ubuntu 16.04 support (thanks kamejoko80) <Florent Kermarrec>
    * | | 80c3dc41 - targets: use mem_region.origin instead of mem_map definition (prepare for automatic mem_region allocation) <Florent Kermarrec>
    * | | 53bc18cc - soc_core: add new alloc_mem/add_mem_region to allow automatic allocation of memory regions <Florent Kermarrec>
    |/ /
    * | eae0e004 - cores/clock/xadc: ease DRP timings <bunnie>
    * | 7b92a17c - test/test_targets: limit max_sdram_size to 1GB <Florent Kermarrec>
    * | 008a0894 - targets/nexys4ddr: fix typo <Florent Kermarrec>
    * | 36e5274a - SoCSDRAM: set default max_sdram_size to 1GB (maximum we can map with current mem_map) <Florent Kermarrec>
    * | 46c1c5c1 - targets/kcu105: remove main_ram_size_limit <Florent Kermarrec>
    * | 5913c91c - SoCSDRAM: rename main_ram_size_limit to max_sdram_size and make it a parameter of SoCSDRAM, expose SoCSDRAM parameters to user <Florent Kermarrec>
    * | 1c465f89 - build/lattice: add add_false_path_constraint method for API compatibility but false paths are not yet used/translated to .lpf file <Florent Kermarrec>
    * | b4ba2a47 - soc/cores/uart: set rx_fifo_rx_we to True on UARTCrossover <Florent Kermarrec>
    |/
    * 5aa516cb - soc/cores/uart: add rx_fifo_rx_we parameter to pulse rx_fifo.source.ready on rxtx register read. <Florent Kermarrec>
    * 862e784e - cpu/vexriscv: use 32-bit signal for externalResetVector <Florent Kermarrec>
    * f2a1673f - targets/arty/genesys2: fix EthernetSoC/EtherboneSoC selection <Florent Kermarrec>
    * 990870d0 - targets/genesys2: add EtherboneSoC <Florent Kermarrec>
    * 820e79bf - platforms/de0nano: specify gpio for serial <Florent Kermarrec>
    * ba366d42 - targets: cleanup EthernetSoC <Florent Kermarrec>
    * a2685370 - soc/interconnect/packet/Depacketizer: use both sink.valid and sink.ready to update sink_d, fix Etherbone regression on Arty. <Florent Kermarrec>
    * a168ecba - targets/arty: add EtherboneSoC <Florent Kermarrec>
    * 7a4ecfa5 - targets/kcu105: update <Florent Kermarrec>
    * 68e225fb - test/test_targets: update <Florent Kermarrec>
    * 42efa998 - SoCCore: set default integrated_rom/ram_size to 0. For targets, defaults values are provided by soc_core_args. <Florent Kermarrec>
    * 4050e608 - SoCCore: use hex for integrated_rom/sram_size <Florent Kermarrec>
    *   f818755c - Merge pull request #339 from gsomlo/gls-csr-cleanup <enjoy-digital>
    |\
    | * b073ebad - bios/sdram: switch to updated CSR accessors, and misc. cleanup <Gabriel Somlo>
    | * 2c393041 - software, integration/export: rename and reimplement CSR accessors <Gabriel Somlo>
    * | f1606dbc - tools/litex_sim: use default integrated_rom_size <Florent Kermarrec>
    * | 4648db0c - cores/uart/UARTInterface: remove connect method <Florent Kermarrec>
    * | 6c9f418d - soc_core: fix uart stub <Florent Kermarrec>
    |/
    * 63cd23c9 - cpu/vexriscv: revert mem_map_linux/main_ram <Florent Kermarrec>
    * 83a7225c - SoCCore: set integrated rom/sram size default values in soc_core_args and use it in targets <Florent Kermarrec>
    * 6e3f25a7 - cpu/vexriscv/mem_map_linux: update main_ram to 0x40000000 <Florent Kermarrec>
    * fe14b9cf - targets/genesys2: update self.register_sdram <Florent Kermarrec>
    * 39ce39a2 - soc_sdram: add l2_data_width parameter to set minimal l2_data_width to improve DRAM accesses efficiency. <Florent Kermarrec>
    * 23175190 - cores/uart: add UARTCrossover <Florent Kermarrec>
    * 2f03d323 - cores/uart/UART: add stream interface (phy=None), add connect method and use this for UART Stub/Crossover. <Florent Kermarrec>
    * d92bd8ff - gen/fhdl/verilog: fix signed init values <Florent Kermarrec>
    *   ff066a5e - Merge pull request #338 from DurandA/master <enjoy-digital>
    |\
    | * d24a4b54 - Add optional 'ignore-loops' flag to nextpnr <Arnaud Durand>
    * | 26fe45fc - cores/uart: rename BridgedUART to UARTEmulator and rework/simplify it. Also integrated it in SoCCore with uart_name="emulator" <Florent Kermarrec>
    * |   d40bf9d8 - Merge pull request #340 from xobs/bridged-uart <enjoy-digital>
    |\ \
    | |/
    |/|
    | * 5079a3c3 - uart: add BridgedUart <Sean Cross>
    |/
    * f70dd482 - bios/sdram: add memspeed <Florent Kermarrec>
    * fa22d6aa - wishbone/Cache: avoid REFILL_WRTAG state to improve speed. <Florent Kermarrec>
    * f408527d - soc/cores/cpu: add riscv64-linux toolchain support for risc-v cpus. <Florent Kermarrec>
    * 8889821c - targets: sync with litex-boards <Florent Kermarrec>
    * aba8fc5c - build/altera/quartus: allow multiple call of add_period_constraint if constraint is similar. <Florent Kermarrec>
    *   e318287e - Merge pull request #337 from gregdavill/spi-flash <enjoy-digital>
    |\
    | * 49781467 - soc/cores/spi_flash: Don't tristate DQ2/DQ3 when bitbanging <Greg Davill>
    * | 2cf95e9f - platforms/minispartan6: rename sd to sdcard and regroup data lines <Florent Kermarrec>
    * | e99740e8 - platforms/nexys4ddr: add sdcard pins <Florent Kermarrec>
    * | 83ad674f - build/lattice/trellis: use a single fonction to parse device <Florent Kermarrec>
    * |   018c7ca8 - Merge pull request #336 from kbeckmann/trellis-speed <enjoy-digital>
    |\ \
    | * | 426ab676 - trellis: Pass speed grade argument to nextpnr <Konrad Beckmann>
    |/ /
    * |   fd4cbd80 - Merge pull request #331 from betrusted-io/xadc_mods <enjoy-digital>
    |\ \
    | * | 378722a7 - soc/cores/xadc: define analog_layout and simplify analog_pads connections <Florent Kermarrec>
    | * | 87d456ca - bring back analog_pads specifier, remove reset conditions on VP <bunnie>
    | * | 4dc0a614 - soc/core/xadc: cleanup, simplify and add expose_drp method - keep CSR ordering with older version, requested for software compatibility. - always enable analog capability (user will just not use it if not needed). - add expose_drp method (similar to clock.py) for cases where DRP is needed. <Florent Kermarrec>
    | * | 5eec7432 - fix a couple bugs in the DRP readout path <bunnie>
    | * | 56ccaeeb - add support for DRP on XADC <bunnie>
    * | | 642d0737 - cpu/minerva: fix variant syntax warning <Florent Kermarrec>
    * | |   8ba204c7 - Merge pull request #332 from gsomlo/gls-csr-mem-sel <enjoy-digital>
    |\ \ \
    | * | | d087e2e0 - interconnect/csr_bus/SRAM: allow 64-bit alignment (on 64-bit CPUs) <Gabriel Somlo>
    |/ / /
    * | | 690de79d - cpu/microwatt: reorder sources, add comments <Florent Kermarrec>
    * | | e36df2a6 - build/lattice/icestorm: increase similarities with trellis. <Florent Kermarrec>
    * | | 197edad3 - soc/integration/soc_core/SoCController: specify initial reset value of scratch register in description <Florent Kermarrec>
    * | | b65a36e7 - soc/integration/soc_core/SoCController: rephrase CSR descriptions a bit <Florent Kermarrec>
    * | |   1f27b21f - Merge pull request #330 from xobs/document-ctrl-timer0 <enjoy-digital>
    |\ \ \
    | * | | c5aa929d - cores: timer: clean up wording for timer documentation <Sean Cross>
    | * | | 2d75aee7 - soc_core: ctrl: document registers <Sean Cross>
    | * | | a251d712 - cores: timer: fix documentation formatting <Sean Cross>
    |/ / /
    * | | db7a48c0 - soc/cores/clock: also allow margin=0 on iCE40PLL and ECP5PLL <Florent Kermarrec>
    * | | caacc411 - Merge pull request #328 from betrusted-io/precise_clocks <enjoy-digital>
    |\| |
    | * | 219bb7f2 - add the possibility for a "precise" clock solution <bunnie>
    |/ /
    * | 9336fe11 - build/microsemi/libero_soc: update add_period_constraint behavior when clock is already constrainted. <Florent Kermarrec>
    * | 3022f02b - build/xilinx/vivado: update add_period_constraint behavior when clock is already constrainted. <Florent Kermarrec>
    * | fe4eaf58 - build/lattice/icestorm/add_period_constraint: improve <Florent Kermarrec>
    * | 6b91e882 - soc/integration/builder: avoid try/except on LiteDRAM import, just check if SoC has an sdram and do the import if so <Florent Kermarrec>
    * |   2157d0f3 - Merge pull request #327 from zakgi/master <enjoy-digital>
    |\ \
    | * | 39ae230b - moving RAM offsets outside of CSR_ETHMAC define <Giammarco Zacheo>
    * | | f0b5c672 - Allow specifying the same clock constraint multiple times. <Tim 'mithro' Ansell>
    * | | 8b955e6f - Allow LiteX builder to be used without LiteDRAM. <Tim 'mithro' Ansell>
    * | | a738739a - Improve the invalid CPU type error message. <Tim 'mithro' Ansell>
    * | | 85ade2b3 - build/xilinx/programmer: fix vivado_cmd when settings are sourced manually. <Florent Kermarrec>
    |/ /
    * |   ffa7ca8f - Merge pull request #321 from gsomlo/gls-rocket-aximem-wide <enjoy-digital>
    |\ \
    | * | cd8feca5 - cpu/rocket: variants with double (128b) and quad (256b) wide mem_axi <Gabriel Somlo>
    * | |   e754c055 - Merge pull request #319 from DurandA/feature-integer-attributes <enjoy-digital>
    |\ \ \
    | |/ /
    |/| |
    | * | 94e239ff - Add integer attributes <Arnaud Durand>
    | * | f8c58216 - Revert "gen/fhdl/verilog: allow single element verilog inline attribute" <Arnaud Durand>
    * | |   40c35550 - Merge pull request #320 from gsomlo/gls-touch-up <enjoy-digital>
    |\ \ \
    | * | | 585b50b2 - soc_core: csr_alignment assertions <Gabriel Somlo>
    | * | | b6818c20 - cpu/rocket: access PLIC registers via pointer dereference <Gabriel Somlo>
    |/ / /
    * / / 0e46913d - cpu/microwatt: add initial software support <Florent Kermarrec>
    |/ /
    * | f883f0c7 - cpu/microwatt: add submodule <Florent Kermarrec>
    * | 5da0bcbd - cpu/microwatt: set csr to 0xc0000000 (IO region) <Florent Kermarrec>
    * | 39a8ebe7 - cpu/microwatt: fix add_source/add_sources <Florent Kermarrec>
    * | d74a7463 - soc/cores/pwm: remove debug print(n) <Florent Kermarrec>
    * | bd15f07c - platforms/netv2: add xc7a100t support <Florent Kermarrec>
    * | 76e57414 - platforms/minispartan6: add assert on available devices <Florent Kermarrec>
    * | bfe0bf64 - cpu/microwatt: simplify add_sources <Florent Kermarrec>
    * | b9edde20 - cpu/microwatt: add io_regions and gcc_flags <Florent Kermarrec>
    * | 16e7c6b6 - cpu/microwatt: update copyright <Florent Kermarrec>
    * | 3d79324f - cpu/microwatt: drive stall signal (no burst support) <Florent Kermarrec>
    * | da3a178b - soc/cores/pwm: add clock_domain support <Florent Kermarrec>
    * | 9da28c4e - build/xilinx/XilinxMultiRegImpl: fix n=0 case <Florent Kermarrec>
    * | ec7dc2d8 - build/xilinx/ise: cleanup/simplify pass, remove mist support (not aware of anyone using it) <Florent Kermarrec>
    * | 1b963bb2 - soc/cores/cpu: add initial Microwatt gateware support <Florent Kermarrec>
    * | c34255d2 - soc/cores/cpu/minerva: add self.reset to i_rst <Florent Kermarrec>
    * |   8b6f9e0a - Merge pull request #315 from gsomlo/gls-csr-assert <enjoy-digital>
    |\ \
    | * | a0dad1b0 - soc_core: additional CSR safety assertions <Gabriel Somlo>
    |/ /
    * | fb6b0786 - soc_core: remove static 16MB csr region allocation (use csr_address_width to allocate the correct size) <Florent Kermarrec>
    * | b1a1e5e2 - soc_core: add sort of CSR regions by origin (allow csr.h/csr.csv to be ordered by origin) <Florent Kermarrec>
    * | 061d593d - cores/8b10b: use real Memory for 6b5b table (to improve timings on ECP5) <Florent Kermarrec>
    * | a0122f98 - build/xilinx/vivado: move build_script generation <Florent Kermarrec>
    * | 18ff8f38 - build/xilinx/vivado: cleanup/simplify <Florent Kermarrec>
    * | 0931ccc9 - build/lattice/icestorm: cleanup/simplify (and remove arachne-pnr support) <Florent Kermarrec>
    * | b1b92053 - build/xilinx/common/platform/programmer: cleanup pass <Florent Kermarrec>
    * | edaa66bb - boards: add Lambdaconcept's PCIe Screamer (R02) <Florent Kermarrec>
    * | a8635c48 - targets/versa_ecp5: fix compilation with diamond <Florent Kermarrec>
    * | 30a18808 - boards/targets: keep attributes are no longer needed since automatically added when applying constraints to signals. <Florent Kermarrec>
    * | 23c33cfa - build: automatically add keep attribute to signals with timing constraints. <Florent Kermarrec>
    * | 4c9af635 - build/altera/quartus: allow adding period constraints on nets and add optional additional sdc/qsf commands <Florent Kermarrec>
    * | 22e6f5ac - build/lattice/trellis: nextpnr now handle LPF timing constraints and multiple clock domains, freq_constraint is no longer needed. <Florent Kermarrec>
    * | 8fb3f9a9 - build/lattice: cleanup/simplify (no functional changes) <Florent Kermarrec>
    * | 946478a7 - build/lattice: cleanup/simplify <Florent Kermarrec>
    * | 60edca23 - build/microsemi: cleanup/simplify (no functional change) <Florent Kermarrec>
    * | 50fdc5ce - build/altera: cleanup/simplify (no functional change) <Florent Kermarrec>
    * |   b17dfafa - Merge pull request #313 from mmicko/yosys_ise_flow_fix <Tim Ansell>
    |\ \
    | * | 783dfa50 - Properly select family for those currently supported <Miodrag Milanovic>
    | * | 6560911d - Integrate with latest yosys changes <Miodrag Milanovic>
    * | | 8d90f4e9 - build/xilinx/vivado: use VHDL 2008 as default <Florent Kermarrec>
    * | | cfd17321 - targets/nexys4ddr: remove MEMTEST_ADDR_SIZE limitation (no longer needed) <Florent Kermarrec>
    * | | 201d60f3 - targets/netv2: switch to MVP DDR3 (K4B2G1646F instead of MT41J128M16) <Florent Kermarrec>
    * | | 6b820647 - targets: uniformize, improve presentation <Florent Kermarrec>
    * | | 718f6995 - README: fix LitePCIe Travis-CI link <Florent Kermarrec>
    * | | 6de20f18 - soc/interconnect/csr: add fields support for CSRStorage's write simulation method <Florent Kermarrec>
    * | | 2567a0ae - soc/cores/gpio: add GPIO Tristate <Florent Kermarrec>
    * | | d702c0fe - setup.py: update long_description <Florent Kermarrec>
    * | | c9665aed - README.md: use litex logo <Florent Kermarrec>
    * | | 82819dd5 - README: switch to Markdown <Florent Kermarrec>
    * | |   90f9ffc5 - Merge pull request #311 from kbeckmann/trellis_cabga256 <Tim Ansell>
    |\ \ \
    | |/ /
    |/| |
    | * | f411d6d3 - trellis: Support the CABGA256 package <Konrad Beckmann>
    |/ /
    * |   3d20442f - Merge pull request #310 from xobs/spi-flash-mode3-doc <enjoy-digital>
    |\ \
    | |/
    |/|
    | * 581c2372 - spi_flash: correct documentation on SPI mode <Sean Cross>
    |/
    * de205d4a - tools/remote/comm_udp: only use one socket <Florent Kermarrec>
    * bdaca40f - build/generic_platform: avoid duplicate in GenericPlatform.sources <Florent Kermarrec>
    * 6883a436 - soc/cores/clock: change drp_locked to CSRStatus and connect it :) <Florent Kermarrec>
    * 36107cdf - soc/cores/clock: reset PLL/MMCM on all 7-series/Ultrascale with self.reset signal <Florent Kermarrec>
    *   e8e70b16 - Merge pull request #309 from antmicro/mmcm-fix <enjoy-digital>
    |\
    | * fd14b765 - soc/cores/clock: add lock reg and assign reset <Pawel Czarnecki>
    * 04017519 - soc/interconnect/axi: add Wishbone2AXILite <Florent Kermarrec>
    * 4b073a44 - test/test_axi: cosmetic <Florent Kermarrec>
    * d9055211 - build/tools/get_migen/litex_git_revision: avoid git fatal error message is not installed as a git repository <Florent Kermarrec>

 * migen changed from 0.6.dev-328-gd11565a to 0.6.dev-335-g3f9809b
    * 3f9809b - platforms: add zc706 + coraz7_07s <Astro>
    * e2e6c72 - sayma: sata -> fat_pipe <Sebastien Bourdeauducq>
    * 7a54c79 - metlino: add ddmtd_helper_clk <Sebastien Bourdeauducq>
    * 56e1b4e - metlino: add DCXO control signals <Sebastien Bourdeauducq>
    * 084e2a2 - metlino: add clock muxes <Sebastien Bourdeauducq>
    * 4d4d055 - metlino: add SFPs <Sebastien Bourdeauducq>
    * 2480d49 - metlino: fix clk200 <Sebastien Bourdeauducq>

 * nmigen changed from f207f3f to 8f5a253
    * 8f5a253 - rm travis-ci <Sebastien Bourdeauducq>
    * 63a53fa - Revert "setup: update project URLs." <Sebastien Bourdeauducq>
    *   b2d924e - Merge remote-tracking branch 'wq/master' <Sebastien Bourdeauducq>
    |\
    | * 12c7902 - vendor: fix a few issues in commit 2f8669ca. <whitequark>
    | * 2f8669c - lib.cdc: extract AsyncFFSynchronizer. <awygle>
    | * a14a572 - hdl.ast: fix off-by-1 in Initial.__init__(). <whitequark>
    | * ec7aee6 - back.pysim: fix RHS codegen for Cat() and Repl(..., 0). <whitequark>
    | * 377f2d9 - back.pysim: optionally allow introspecting generated code. <whitequark>
    | * 5ae8791 - nmigen.compat.genlib.cdc: add PulseSynchronizer. <awygle>
    | * fcbabfe - nmigen.lib.cdc: port PulseSynchronizer. <awygle>
    | * 71d9eea - Travis: prune dependencies. <whitequark>
    | * 3fd7fe7 - Travis: test on Python 3.8. <whitequark>
    | * 57b08db - cli: update use of deprecated code. <whitequark>
    | * 8947096 - back.pysim: accept write_vcd(vcd_file=None). <whitequark>
    | * 38aa9fb - setup: update project URLs. <whitequark>
    | * 4f17cb1 - doc: remove outdated files and references to them. <whitequark>
    | * 66f4510 - README: link to IRC channel. <whitequark>
    | * 36f498e - README: consolidate requirements in the Installation section. <whitequark>
    | * 3b67271 - test_build_res: fix after commit 3e2ecdf2. <whitequark>
    | * 3e2ecdf - build.res,vendor: place clock constraint on port, not net, if possible. <whitequark>
    | * 5888f29 - xilinx_{7series,ultrascale}: run `report_methodology`. <whitequark>
    | * 27b47fa - hdl.ast: add Value.{as_signed,as_unsigned}. <whitequark>
    | * 9301e31 - test_lib_fifo: define all referenced FSM states. <whitequark>
    | * a1c5863 - hdl.dsl: make referencing undefined FSM states an error. <whitequark>
    | * 97cc78a - hdl.ir: type check ports. <whitequark>
    | * 882fddf - back.pysim: emit toplevel inputs in VCD files as well. <whitequark>
    | * d3775ee - back.pysim: make `write_vcd(traces=)` actually use those traces. <whitequark>
    | * 3df4297 - hdl.dsl: reject name mismatch in `m.domains.<name> +=`. <whitequark>
    | * 86b57fe - hdl.dsl: type check when adding to m.domains. <whitequark>
    | * 31cd72c - hdl.mem: add synthesis attribute support. <whitequark>
    | * f7abe36 - hdl.mem: document Memory. <whitequark>
    * | 57d95b7 - Merge branch 'master' of https://github.com/nmigen/nmigen <Sebastien Bourdeauducq>
    |\|
    | * dfcf793 - hdl.{ast,dsl}: allow whitespace in bit patterns. <whitequark>
    * | 7245b1e - Update README. <Sebastien Bourdeauducq>
    * | 60447a0 - Merge branch 'master' of https://github.com/nmigen/nmigen <Sebastien Bourdeauducq>
    |\|
    | * a295e35 - hdl.ast: update documentation for Signal. <whitequark>
    | * 49758a3 - hdl.ast: prohibit shifts by signed value. <whitequark>
    | * cce6b86 - build.plat: align pipeline with Fragment.prepare(). <whitequark>
    | * 6fd7cba - hdl.dsl: don't allow inheriting from Module. <whitequark>
    | * afece15 - hdl.ast: warn on unused property statements (Assert, Assume, etc). <whitequark>
    | * 9fb4a4f - _unused: extract must-use logic from hdl.ir. <whitequark>
    | * 687d3a3 - hdl.dsl: add missing case width check for Enum values. <whitequark>
    | * a9da9ef - README: clarify relationship to Migen. <whitequark>
    | * 9964fc6 - hdl.dsl: make `if m.{If,Elif,Else}(...)` a syntax error. <whitequark>
    | * 3ac13eb - back.rtlil: don't emit wires for empty signals. <whitequark>
    | * b72c3fc - vendor.lattice_ecp5: support internal oscillator (OSCG). <Mike Walters>
    | * ec3a219 - build.dsl: allow strings to be used as connector numbers. <Jaro Habiger>
    | * 7792a6c - vendor.lattice_{ice40,ecp5}: Support .il (RTLIL) files in extra_files <Sylvain Munaut>
    | * c280c7c - Update README. <whitequark>
    * | c42c3a0 - vendor.lattice_{ice40,ecp5}: Support .il (RTLIL) files in extra_files <Sylvain Munaut>
    |/
    * a7be3b4 - hdl.ir: resolve hierarchy conflicts before creating missing domains. <whitequark>
    * 7cb3095 - hdl.xfrm: transform drivers as well in DomainRenamer. <whitequark>
    * e18385b - Remove everything deprecated in nmigen 0.1. <whitequark>
    * e4e2671 - Signal: allow to use integral Enum for reset value. <Staf Verhaegen>
    * 8184efd - vendor.intel: fix output enable width for XDR=0 case. <schwigi>
    * 63902dd - build.run: fix indentation. <Alain Péteut>
    * 476ce15 - back.rtlil: do not consider unreachable array elements when legalizing. <whitequark>
    * 318274d - hdl.mem: fix src_loc_at in ReadPort, WritePort. <whitequark>
    * 6765021 - hdl.ast: Fix width for unary minus operator on signed argument. <Marcin Kościelnicki>
    * 7650431 - back.pysim: fix miscompilation of Signal(unsigned) - Signal(signed). <whitequark>
    * d048f06 - hdl.ast: actually remove simulator commands. <whitequark>
    * 72cfdb0 - vendor.intel: silence meaningless warnings in nMigen files <Dan Ravensloft>
    * 7df7005 - back.pysim: redesign the simulator. <whitequark>
    * f8428ff - back.rtlil: infer bit width for instance parameters. <whitequark>
    * 56bb42a - hdl.ir: for instance ports, prioritize defs over uses. <whitequark>

Full submodule status
--
 3a6108a75be356a3dc53760d22782f1323248b6b edid-decode (heads/master)
 3a06aa84b62ad24467fb0d2c6ceddf565e9ea447 flash_proxies (heads/master)
 4cfbc71fc2e2561e82c984c074094a297c9d32e8 litedram (remotes/origin/HEAD)
 32d4af1148d59939fdf04b4ba319c83427b698c3 liteeth (remotes/origin/HEAD)
 b544659f23f442963f3f0d56061ff76fd432ac7f litepcie (remotes/origin/HEAD)
 1e3573b07d382eac50ef764fd839009bf90cb8ce litesata (heads/master)
 b3d1e6938f42045ade1fcb10aa2498722a4ea041 litescope (remotes/origin/HEAD)
 7457a29b1a47fe15e81fa37f3bbdd510788f1d53 liteusb (heads/master)
 49d812694951a924617d8e429d72c0d4da96372a litevideo (remotes/origin/HEAD)
 536ae0e619e3d9820f4e9ff8f33dc2829bc68398 litex (remotes/origin/HEAD)
-84164f8fab5c65e2dd828ed20422d14026f5b140 litex-boards
 2ed761f4c138f0237a7dca8d8dd45cea0b3c24d1 litex-renode (remotes/origin/HEAD)
 3f9809b0ea62b26f6c99f1b5221b22f8255bc1f6 migen (0.6.dev-335-g3f9809b)
 8f5a253b22cd4ebcd56304a3662f4c70e3b34ed5 nmigen (v0.1-69-g8f5a253)