analogdevicesinc · IuliaCMoldovan · Sep 7, 2023 · Aug 18, 2023 · Aug 18, 2023 · Aug 17, 2023
diff --git a/LICENSE_ADIBSD b/LICENSE_ADIBSD
@@ -1,5 +1,7 @@
 Copyright (C) 2011-2023 Analog Devices, Inc. All rights reserved.
 
+SPDX short identifier: ADIBSD
+
 Redistribution and use in source and binary forms, with or without modification,
 are permitted provided that the following conditions are met:
     - Redistributions of source code must retain the above copyright

diff --git a/library/jesd204/README.md → LICENSE_ADIJESD204 b/library/jesd204/README.md → LICENSE_ADIJESD204
@@ -1,14 +1,12 @@
-# Analog Devices JESD204B HDL Support
-
-## Licensing
+SPDX short identifier: ADIJESD204
 
 The ADI JESD204 Core is released under the following license, which is
 different than all other HDL cores in this repository.
 
 Please read this, and understand the freedoms and responsibilities you have by
 using this source code/core.
 
-The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
+The JESD204 HDL, is copyright (c) 2016-2023 Analog Devices Inc.
 
 This core is free software, you can use run, copy, study, change, ask questions
 about and improve this core. Distribution of source, or resulting binaries
@@ -22,13 +20,13 @@ WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A
 PARTICULAR PURPOSE. See the GNU General Public License for more details.
 
 You should have received a copy of the GNU General Public License version 2
-along with this source code, and binary.  If not, see
+along with this source code, and binary. If not, see
 <http://www.gnu.org/licenses/>.
 
 Commercial licenses (with commercial support) of this JESD204 core are also
-available under terms different than the General Public License. (e.g. they do
+available under terms different than the General Public License (e.g. they do
 not require you to accompany any image (FPGA or ASIC) using the JESD204 core
-with any corresponding source code.) For these alternate terms you must
+with any corresponding source code). For these alternate terms you must
 purchase a license from Analog Devices Technology Licensing Office. Users
 interested in such a license should contact [email protected] for
 more information. This commercial license is sub-licensable (if you purchase
@@ -39,24 +37,6 @@ to use this core in a commercial setting without releasing their source code).
 In addition, we kindly ask you to acknowledge ADI in any program, application
 or publication in which you use this JESD204 HDL core. (You are not required to
 do so; it is up to your common sense to decide whether you want to comply with
-this request or not.) For general publications, we suggest referencing : “The
+this request or not.) For general publications, we suggest referencing: "The
 design and implementation of the JESD204 HDL Core used in this project is
-copyright © 2016-2017, Analog Devices, Inc.”
-
-## Support
-
-Analog Devices will provide limited online support for anyone using the core
-with Analog Devices components (ADC, DAC, Clock, etc) via
-https://ez.analog.com/community/fpga under the GPL license. If you would like
-deterministic support when using this core with an ADI component, please
-investigate a commercial license. Using a non-ADI JESD204 device with this core
-is possible under the GPL, but Analog Devices will not help with issues you may
-encounter.
-
-## Documenation
-
- - [JESD204B/C overview](https://wiki.analog.com/resources/fpga/peripherals/jesd204)
- - [Analog Devices JESD204B/C Transmit Peripheral](https://wiki.analog.com/resources/fpga/peripherals/jesd204/axi_jesd204_tx)
- - [Analog Devices JESD204B/C Receive Peripheral](https://wiki.analog.com/resources/fpga/peripherals/jesd204/axi_jesd204_rx)
-
-
+copyright (c) 2016-2023, Analog Devices, Inc."
diff --git a/library/common/tb/tb_base.v b/library/common/tb/tb_base.v
@@ -1,46 +1,37 @@
+// ***************************************************************************
+// ***************************************************************************
+// Copyright (C) 2017-2023 Analog Devices, Inc. All rights reserved.
 //
-// The ADI JESD204 Core is released under the following license, which is
-// different than all other HDL cores in this repository.
+// In this HDL repository, there are many different and unique modules, consisting
+// of various HDL (Verilog or VHDL) components. The individual modules are
+// developed independently, and may be accompanied by separate and unique license
+// terms.
 //
-// Please read this, and understand the freedoms and responsibilities you have
-// by using this source code/core.
+// The user should read each of these license terms, and understand the
+// freedoms and responsibilities that he or she has by using this source/core.
 //
-// The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
-//
-// This core is free software, you can use run, copy, study, change, ask
-// questions about and improve this core. Distribution of source, or resulting
-// binaries (including those inside an FPGA or ASIC) require you to release the
-// source of the entire project (excluding the system libraries provide by the
-// tools/compiler/FPGA vendor). These are the terms of the GNU General Public
-// License version 2 as published by the Free Software Foundation.
-//
-// This core  is distributed in the hope that it will be useful, but WITHOUT ANY
+// This core is distributed in the hope that it will be useful, but WITHOUT ANY
 // WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
-// A PARTICULAR PURPOSE. See the GNU General Public License for more details.
+// A PARTICULAR PURPOSE.
+//
+// Redistribution and use of source or resulting binaries, with or without modification
+// of this file, are permitted under one of the following two license terms:
 //
-// You should have received a copy of the GNU General Public License version 2
-// along with this source code, and binary.  If not, see
-// <http://www.gnu.org/licenses/>.
+//   1. The GNU General Public License version 2 as published by the
+//      Free Software Foundation, which can be found in the top level directory
+//      of this repository (LICENSE_GPL2), and also online at:
+//      <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
 //
-// Commercial licenses (with commercial support) of this JESD204 core are also
-// available under terms different than the General Public License. (e.g. they
-// do not require you to accompany any image (FPGA or ASIC) using the JESD204
-// core with any corresponding source code.) For these alternate terms you must
-// purchase a license from Analog Devices Technology Licensing Office. Users
-// interested in such a license should contact [email protected] for
-// more information. This commercial license is sub-licensable (if you purchase
-// chips from Analog Devices, incorporate them into your PCB level product, and
-// purchase a JESD204 license, end users of your product will also have a
-// license to use this core in a commercial setting without releasing their
-// source code).
+// OR
 //
-// In addition, we kindly ask you to acknowledge ADI in any program, application
-// or publication in which you use this JESD204 HDL core. (You are not required
-// to do so; it is up to your common sense to decide whether you want to comply
-// with this request or not.) For general publications, we suggest referencing :
-// “The design and implementation of the JESD204 HDL Core used in this project
-// is copyright © 2016-2017, Analog Devices, Inc.”
+//   2. An ADI specific BSD license, which can be found in the top level directory
+//      of this repository (LICENSE_ADIBSD), and also on-line at:
+//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      This will allow to generate bit files and not release the source code,
+//      as long as it attaches to an ADI device.
 //
+// ***************************************************************************
+// ***************************************************************************
 
   reg clk = 1'b0;
   reg [3:0] reset_shift = 4'b1111;

diff --git a/library/intel/adi_jesd204/adi_jesd204_glue_hw.tcl b/library/intel/adi_jesd204/adi_jesd204_glue_hw.tcl
@@ -1,46 +1,7 @@
-#
-# The ADI JESD204 Core is released under the following license, which is
-# different than all other HDL cores in this repository.
-#
-# Please read this, and understand the freedoms and responsibilities you have
-# by using this source code/core.
-#
-# The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
-#
-# This core is free software, you can use run, copy, study, change, ask
-# questions about and improve this core. Distribution of source, or resulting
-# binaries (including those inside an FPGA or ASIC) require you to release the
-# source of the entire project (excluding the system libraries provide by the
-# tools/compiler/FPGA vendor). These are the terms of the GNU General Public
-# License version 2 as published by the Free Software Foundation.
-#
-# This core  is distributed in the hope that it will be useful, but WITHOUT ANY
-# WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
-# A PARTICULAR PURPOSE. See the GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License version 2
-# along with this source code, and binary.  If not, see
-# <http://www.gnu.org/licenses/>.
-#
-# Commercial licenses (with commercial support) of this JESD204 core are also
-# available under terms different than the General Public License. (e.g. they
-# do not require you to accompany any image (FPGA or ASIC) using the JESD204
-# core with any corresponding source code.) For these alternate terms you must
-# purchase a license from Analog Devices Technology Licensing Office. Users
-# interested in such a license should contact [email protected] for
-# more information. This commercial license is sub-licensable (if you purchase
-# chips from Analog Devices, incorporate them into your PCB level product, and
-# purchase a JESD204 license, end users of your product will also have a
-# license to use this core in a commercial setting without releasing their
-# source code).
-#
-# In addition, we kindly ask you to acknowledge ADI in any program, application
-# or publication in which you use this JESD204 HDL core. (You are not required
-# to do so; it is up to your common sense to decide whether you want to comply
-# with this request or not.) For general publications, we suggest referencing :
-# “The design and implementation of the JESD204 HDL Core used in this project
-# is copyright © 2016-2017, Analog Devices, Inc.”
-#
+###############################################################################
+## Copyright (C) 2016, 2018, 2019, 2020, 2021, 2022 Analog Devices, Inc. All rights reserved.
+### SPDX short identifier: ADIJESD204
+###############################################################################
 
 package require qsys 14.0
 source ../../../scripts/adi_env.tcl

diff --git a/library/intel/adi_jesd204/adi_jesd204_hw.tcl b/library/intel/adi_jesd204/adi_jesd204_hw.tcl
@@ -1,46 +1,7 @@
-#
-# The ADI JESD204 Core is released under the following license, which is
-# different than all other HDL cores in this repository.
-#
-# Please read this, and understand the freedoms and responsibilities you have
-# by using this source code/core.
-#
-# The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
-#
-# This core is free software, you can use run, copy, study, change, ask
-# questions about and improve this core. Distribution of source, or resulting
-# binaries (including those inside an FPGA or ASIC) require you to release the
-# source of the entire project (excluding the system libraries provide by the
-# tools/compiler/FPGA vendor). These are the terms of the GNU General Public
-# License version 2 as published by the Free Software Foundation.
-#
-# This core  is distributed in the hope that it will be useful, but WITHOUT ANY
-# WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
-# A PARTICULAR PURPOSE. See the GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License version 2
-# along with this source code, and binary.  If not, see
-# <http://www.gnu.org/licenses/>.
-#
-# Commercial licenses (with commercial support) of this JESD204 core are also
-# available under terms different than the General Public License. (e.g. they
-# do not require you to accompany any image (FPGA or ASIC) using the JESD204
-# core with any corresponding source code.) For these alternate terms you must
-# purchase a license from Analog Devices Technology Licensing Office. Users
-# interested in such a license should contact [email protected] for
-# more information. This commercial license is sub-licensable (if you purchase
-# chips from Analog Devices, incorporate them into your PCB level product, and
-# purchase a JESD204 license, end users of your product will also have a
-# license to use this core in a commercial setting without releasing their
-# source code).
-#
-# In addition, we kindly ask you to acknowledge ADI in any program, application
-# or publication in which you use this JESD204 HDL core. (You are not required
-# to do so; it is up to your common sense to decide whether you want to comply
-# with this request or not.) For general publications, we suggest referencing :
-# “The design and implementation of the JESD204 HDL Core used in this project
-# is copyright © 2016-2017, Analog Devices, Inc.”
-#
+###############################################################################
+## Copyright (C) 2016-2023 Analog Devices, Inc. All rights reserved.
+### SPDX short identifier: ADIJESD204
+###############################################################################
 
 package require qsys 14.0
 source ../../../scripts/adi_env.tcl

diff --git a/library/intel/jesd204_phy/jesd204_phy_glue_hw.tcl b/library/intel/jesd204_phy/jesd204_phy_glue_hw.tcl
@@ -1,46 +1,7 @@
-#
-# The ADI JESD204 Core is released under the following license, which is
-# different than all other HDL cores in this repository.
-#
-# Please read this, and understand the freedoms and responsibilities you have
-# by using this source code/core.
-#
-# The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
-#
-# This core is free software, you can use run, copy, study, change, ask
-# questions about and improve this core. Distribution of source, or resulting
-# binaries (including those inside an FPGA or ASIC) require you to release the
-# source of the entire project (excluding the system libraries provide by the
-# tools/compiler/FPGA vendor). These are the terms of the GNU General Public
-# License version 2 as published by the Free Software Foundation.
-#
-# This core  is distributed in the hope that it will be useful, but WITHOUT ANY
-# WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
-# A PARTICULAR PURPOSE. See the GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License version 2
-# along with this source code, and binary.  If not, see
-# <http://www.gnu.org/licenses/>.
-#
-# Commercial licenses (with commercial support) of this JESD204 core are also
-# available under terms different than the General Public License. (e.g. they
-# do not require you to accompany any image (FPGA or ASIC) using the JESD204
-# core with any corresponding source code.) For these alternate terms you must
-# purchase a license from Analog Devices Technology Licensing Office. Users
-# interested in such a license should contact [email protected] for
-# more information. This commercial license is sub-licensable (if you purchase
-# chips from Analog Devices, incorporate them into your PCB level product, and
-# purchase a JESD204 license, end users of your product will also have a
-# license to use this core in a commercial setting without releasing their
-# source code).
-#
-# In addition, we kindly ask you to acknowledge ADI in any program, application
-# or publication in which you use this JESD204 HDL core. (You are not required
-# to do so; it is up to your common sense to decide whether you want to comply
-# with this request or not.) For general publications, we suggest referencing :
-# “The design and implementation of the JESD204 HDL Core used in this project
-# is copyright © 2016-2017, Analog Devices, Inc.”
-#
+###############################################################################
+## Copyright (C) 2016-2022 Analog Devices, Inc. All rights reserved.
+### SPDX short identifier: ADIJESD204
+###############################################################################
 
 package require qsys 14.0
 source ../../../scripts/adi_env.tcl

diff --git a/library/intel/jesd204_phy/jesd204_phy_hw.tcl b/library/intel/jesd204_phy/jesd204_phy_hw.tcl
@@ -1,46 +1,7 @@
-#
-# The ADI JESD204 Core is released under the following license, which is
-# different than all other HDL cores in this repository.
-#
-# Please read this, and understand the freedoms and responsibilities you have
-# by using this source code/core.
-#
-# The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
-#
-# This core is free software, you can use run, copy, study, change, ask
-# questions about and improve this core. Distribution of source, or resulting
-# binaries (including those inside an FPGA or ASIC) require you to release the
-# source of the entire project (excluding the system libraries provide by the
-# tools/compiler/FPGA vendor). These are the terms of the GNU General Public
-# License version 2 as published by the Free Software Foundation.
-#
-# This core  is distributed in the hope that it will be useful, but WITHOUT ANY
-# WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
-# A PARTICULAR PURPOSE. See the GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License version 2
-# along with this source code, and binary.  If not, see
-# <http://www.gnu.org/licenses/>.
-#
-# Commercial licenses (with commercial support) of this JESD204 core are also
-# available under terms different than the General Public License. (e.g. they
-# do not require you to accompany any image (FPGA or ASIC) using the JESD204
-# core with any corresponding source code.) For these alternate terms you must
-# purchase a license from Analog Devices Technology Licensing Office. Users
-# interested in such a license should contact [email protected] for
-# more information. This commercial license is sub-licensable (if you purchase
-# chips from Analog Devices, incorporate them into your PCB level product, and
-# purchase a JESD204 license, end users of your product will also have a
-# license to use this core in a commercial setting without releasing their
-# source code).
-#
-# In addition, we kindly ask you to acknowledge ADI in any program, application
-# or publication in which you use this JESD204 HDL core. (You are not required
-# to do so; it is up to your common sense to decide whether you want to comply
-# with this request or not.) For general publications, we suggest referencing :
-# “The design and implementation of the JESD204 HDL Core used in this project
-# is copyright © 2016-2017, Analog Devices, Inc.”
-#
+###############################################################################
+## Copyright (C) 2016-2022 Analog Devices, Inc. All rights reserved.
+### SPDX short identifier: ADIJESD204
+###############################################################################
 
 package require qsys 14.0