Add copyright & license for all files which need ADI JESD specific li…

…cense

Signed-off-by: Iulia Moldovan <[email protected]>

library/common/tb/tb_base.v

@@ -1,11 +1,14 @@
+// ***************************************************************************
+// ***************************************************************************
+// Copyright (C) 2020-2023 Analog Devices, Inc. All rights reserved.
 //
 // The ADI JESD204 Core is released under the following license, which is
 // different than all other HDL cores in this repository.
 //
 // Please read this, and understand the freedoms and responsibilities you have
 // by using this source code/core.
 //
-// The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
+// The JESD204 HDL, is copyright © 2020-2023 Analog Devices Inc.
 //
 // This core is free software, you can use run, copy, study, change, ask
 // questions about and improve this core. Distribution of source, or resulting
@@ -39,8 +42,7 @@
 // to do so; it is up to your common sense to decide whether you want to comply
 // with this request or not.) For general publications, we suggest referencing :
 // “The design and implementation of the JESD204 HDL Core used in this project
-// is copyright © 2016-2017, Analog Devices, Inc.”
-//
+// is copyright © 2020-2023, Analog Devices, Inc.”
 
   reg clk = 1'b0;
   reg [3:0] reset_shift = 4'b1111;

library/intel/adi_jesd204/adi_jesd204_glue_hw.tcl

@@ -1,11 +1,14 @@
+###############################################################################
+## Copyright (C) 2016-2023 Analog Devices, Inc. All rights reserved.
+### SPDX short identifier: ADIBSD
 #
 # The ADI JESD204 Core is released under the following license, which is
 # different than all other HDL cores in this repository.
 #
 # Please read this, and understand the freedoms and responsibilities you have
 # by using this source code/core.
 #
-# The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
+# The JESD204 HDL, is copyright © 2016-2023 Analog Devices Inc.
 #
 # This core is free software, you can use run, copy, study, change, ask
 # questions about and improve this core. Distribution of source, or resulting
@@ -39,8 +42,7 @@
 # to do so; it is up to your common sense to decide whether you want to comply
 # with this request or not.) For general publications, we suggest referencing :
 # “The design and implementation of the JESD204 HDL Core used in this project
-# is copyright © 2016-2017, Analog Devices, Inc.”
-#
+# is copyright © 2016-2023, Analog Devices, Inc.”
 
 package require qsys 14.0
 source ../../../scripts/adi_env.tcl

library/intel/adi_jesd204/adi_jesd204_hw.tcl

@@ -1,11 +1,14 @@
+###############################################################################
+## Copyright (C) 2016-2023 Analog Devices, Inc. All rights reserved.
+### SPDX short identifier: ADIBSD
 #
 # The ADI JESD204 Core is released under the following license, which is
 # different than all other HDL cores in this repository.
 #
 # Please read this, and understand the freedoms and responsibilities you have
 # by using this source code/core.
 #
-# The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
+# The JESD204 HDL, is copyright © 2016-2023 Analog Devices Inc.
 #
 # This core is free software, you can use run, copy, study, change, ask
 # questions about and improve this core. Distribution of source, or resulting
@@ -39,8 +42,7 @@
 # to do so; it is up to your common sense to decide whether you want to comply
 # with this request or not.) For general publications, we suggest referencing :
 # “The design and implementation of the JESD204 HDL Core used in this project
-# is copyright © 2016-2017, Analog Devices, Inc.”
-#
+# is copyright © 2016-2023, Analog Devices, Inc.”
 
 package require qsys 14.0
 source ../../../scripts/adi_env.tcl

library/intel/jesd204_phy/jesd204_phy_glue_hw.tcl

@@ -1,11 +1,14 @@
+###############################################################################
+## Copyright (C) 2016-2023 Analog Devices, Inc. All rights reserved.
+### SPDX short identifier: ADIBSD
 #
 # The ADI JESD204 Core is released under the following license, which is
 # different than all other HDL cores in this repository.
 #
 # Please read this, and understand the freedoms and responsibilities you have
 # by using this source code/core.
 #
-# The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
+# The JESD204 HDL, is copyright © 2016-2023 Analog Devices Inc.
 #
 # This core is free software, you can use run, copy, study, change, ask
 # questions about and improve this core. Distribution of source, or resulting
@@ -39,8 +42,7 @@
 # to do so; it is up to your common sense to decide whether you want to comply
 # with this request or not.) For general publications, we suggest referencing :
 # “The design and implementation of the JESD204 HDL Core used in this project
-# is copyright © 2016-2017, Analog Devices, Inc.”
-#
+# is copyright © 2016-2023, Analog Devices, Inc.”
 
 package require qsys 14.0
 source ../../../scripts/adi_env.tcl

library/intel/jesd204_phy/jesd204_phy_hw.tcl

@@ -1,11 +1,14 @@
+###############################################################################
+## Copyright (C) 2016-2023 Analog Devices, Inc. All rights reserved.
+### SPDX short identifier: ADIBSD
 #
 # The ADI JESD204 Core is released under the following license, which is
 # different than all other HDL cores in this repository.
 #
 # Please read this, and understand the freedoms and responsibilities you have
 # by using this source code/core.
 #
-# The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
+# The JESD204 HDL, is copyright © 2016-2023 Analog Devices Inc.
 #
 # This core is free software, you can use run, copy, study, change, ask
 # questions about and improve this core. Distribution of source, or resulting
@@ -39,8 +42,7 @@
 # to do so; it is up to your common sense to decide whether you want to comply
 # with this request or not.) For general publications, we suggest referencing :
 # “The design and implementation of the JESD204 HDL Core used in this project
-# is copyright © 2016-2017, Analog Devices, Inc.”
-#
+# is copyright © 2016-2023, Analog Devices, Inc.”
 
 package require qsys 14.0
 

library/jesd204/README.md

@@ -8,7 +8,7 @@ different than all other HDL cores in this repository.
 Please read this, and understand the freedoms and responsibilities you have by
 using this source code/core.
 
-The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
+The JESD204 HDL, is copyright © 2016-2023 Analog Devices Inc.
 
 This core is free software, you can use run, copy, study, change, ask questions
 about and improve this core. Distribution of source, or resulting binaries
@@ -41,7 +41,7 @@ or publication in which you use this JESD204 HDL core. (You are not required to
 do so; it is up to your common sense to decide whether you want to comply with
 this request or not.) For general publications, we suggest referencing : “The
 design and implementation of the JESD204 HDL Core used in this project is
-copyright © 2016-2017, Analog Devices, Inc.”
+copyright © 2016-2023, Analog Devices, Inc.”
 
 ## Support
 

library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_hw.tcl

@@ -1,25 +1,47 @@
-# ***************************************************************************
-# ***************************************************************************
-# Copyright 2018 (c) Analog Devices, Inc. All rights reserved.
+###############################################################################
+## Copyright (C) 2016-2023 Analog Devices, Inc. All rights reserved.
 #
-# Each core or library found in this collection may have its own licensing terms.
-# The user should keep this in in mind while exploring these cores.
+# The ADI JESD204 Core is released under the following license, which is
+# different than all other HDL cores in this repository.
 #
-# Redistribution and use in source and binary forms,
-# with or without modification of this file, are permitted under the terms of either
-#  (at the option of the user):
+# Please read this, and understand the freedoms and responsibilities you have
+# by using this source code/core.
 #
-#   1. The GNU General Public License version 2 as published by the
-#      Free Software Foundation, which can be found in the top level directory, or at:
-# https://www.gnu.org/licenses/old-licenses/gpl-2.0.en.html
+# The JESD204 HDL, is copyright © 2016-2023 Analog Devices Inc.
 #
-# OR
+# This core is free software, you can use run, copy, study, change, ask
+# questions about and improve this core. Distribution of source, or resulting
+# binaries (including those inside an FPGA or ASIC) require you to release the
+# source of the entire project (excluding the system libraries provide by the
+# tools/compiler/FPGA vendor). These are the terms of the GNU General Public
+# License version 2 as published by the Free Software Foundation.
 #
-#   2.  An ADI specific BSD license as noted in the top level directory, or on-line at:
-# https://github.com/analogdevicesinc/hdl/blob/dev/LICENSE
+# This core  is distributed in the hope that it will be useful, but WITHOUT ANY
+# WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
+# A PARTICULAR PURPOSE. See the GNU General Public License for more details.
 #
-# ***************************************************************************
-# ***************************************************************************
+# You should have received a copy of the GNU General Public License version 2
+# along with this source code, and binary.  If not, see
+# <http://www.gnu.org/licenses/>.
+#
+# Commercial licenses (with commercial support) of this JESD204 core are also
+# available under terms different than the General Public License. (e.g. they
+# do not require you to accompany any image (FPGA or ASIC) using the JESD204
+# core with any corresponding source code.) For these alternate terms you must
+# purchase a license from Analog Devices Technology Licensing Office. Users
+# interested in such a license should contact [email protected] for
+# more information. This commercial license is sub-licensable (if you purchase
+# chips from Analog Devices, incorporate them into your PCB level product, and
+# purchase a JESD204 license, end users of your product will also have a
+# license to use this core in a commercial setting without releasing their
+# source code).
+#
+# In addition, we kindly ask you to acknowledge ADI in any program, application
+# or publication in which you use this JESD204 HDL core. (You are not required
+# to do so; it is up to your common sense to decide whether you want to comply
+# with this request or not.) For general publications, we suggest referencing :
+# “The design and implementation of the JESD204 HDL Core used in this project
+# is copyright © 2016-2023, Analog Devices, Inc.”
 
 package require qsys 14.0
 source ../../../scripts/adi_env.tcl

library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_ip.tcl

@@ -1,25 +1,47 @@
-# ***************************************************************************
-# ***************************************************************************
-# Copyright 2018 (c) Analog Devices, Inc. All rights reserved.
+###############################################################################
+## Copyright (C) 2016-2023 Analog Devices, Inc. All rights reserved.
 #
-# Each core or library found in this collection may have its own licensing terms.
-# The user should keep this in in mind while exploring these cores.
+# The ADI JESD204 Core is released under the following license, which is
+# different than all other HDL cores in this repository.
 #
-# Redistribution and use in source and binary forms,
-# with or without modification of this file, are permitted under the terms of either
-#  (at the option of the user):
+# Please read this, and understand the freedoms and responsibilities you have
+# by using this source code/core.
 #
-#   1. The GNU General Public License version 2 as published by the
-#      Free Software Foundation, which can be found in the top level directory, or at:
-# https://www.gnu.org/licenses/old-licenses/gpl-2.0.en.html
+# The JESD204 HDL, is copyright © 2016-2023 Analog Devices Inc.
 #
-# OR
+# This core is free software, you can use run, copy, study, change, ask
+# questions about and improve this core. Distribution of source, or resulting
+# binaries (including those inside an FPGA or ASIC) require you to release the
+# source of the entire project (excluding the system libraries provide by the
+# tools/compiler/FPGA vendor). These are the terms of the GNU General Public
+# License version 2 as published by the Free Software Foundation.
 #
-#   2. An ADI specific BSD license as noted in the top level directory, or on-line at:
-# https://github.com/analogdevicesinc/hdl/blob/dev/LICENSE
+# This core  is distributed in the hope that it will be useful, but WITHOUT ANY
+# WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
+# A PARTICULAR PURPOSE. See the GNU General Public License for more details.
 #
-# ***************************************************************************
-# ***************************************************************************
+# You should have received a copy of the GNU General Public License version 2
+# along with this source code, and binary.  If not, see
+# <http://www.gnu.org/licenses/>.
+#
+# Commercial licenses (with commercial support) of this JESD204 core are also
+# available under terms different than the General Public License. (e.g. they
+# do not require you to accompany any image (FPGA or ASIC) using the JESD204
+# core with any corresponding source code.) For these alternate terms you must
+# purchase a license from Analog Devices Technology Licensing Office. Users
+# interested in such a license should contact [email protected] for
+# more information. This commercial license is sub-licensable (if you purchase
+# chips from Analog Devices, incorporate them into your PCB level product, and
+# purchase a JESD204 license, end users of your product will also have a
+# license to use this core in a commercial setting without releasing their
+# source code).
+#
+# In addition, we kindly ask you to acknowledge ADI in any program, application
+# or publication in which you use this JESD204 HDL core. (You are not required
+# to do so; it is up to your common sense to decide whether you want to comply
+# with this request or not.) For general publications, we suggest referencing :
+# “The design and implementation of the JESD204 HDL Core used in this project
+# is copyright © 2016-2023, Analog Devices, Inc.”
 
 source ../../../scripts/adi_env.tcl
 source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl

library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac_hw.tcl

@@ -1,25 +1,47 @@
-# ***************************************************************************
-# ***************************************************************************
-# Copyright 2018 (c) Analog Devices, Inc. All rights reserved.
+###############################################################################
+## Copyright (C) 2016-2023 Analog Devices, Inc. All rights reserved.
 #
-# Each core or library found in this collection may have its own licensing terms.
-# The user should keep this in in mind while exploring these cores.
+# The ADI JESD204 Core is released under the following license, which is
+# different than all other HDL cores in this repository.
 #
-# Redistribution and use in source and binary forms,
-# with or without modification of this file, are permitted under the terms of either
-#  (at the option of the user):
+# Please read this, and understand the freedoms and responsibilities you have
+# by using this source code/core.
 #
-#   1. The GNU General Public License version 2 as published by the
-#      Free Software Foundation, which can be found in the top level directory, or at:
-# https://www.gnu.org/licenses/old-licenses/gpl-2.0.en.html
+# The JESD204 HDL, is copyright © 2016-2023 Analog Devices Inc.
 #
-# OR
+# This core is free software, you can use run, copy, study, change, ask
+# questions about and improve this core. Distribution of source, or resulting
+# binaries (including those inside an FPGA or ASIC) require you to release the
+# source of the entire project (excluding the system libraries provide by the
+# tools/compiler/FPGA vendor). These are the terms of the GNU General Public
+# License version 2 as published by the Free Software Foundation.
 #
-#   2. An ADI specific BSD license as noted in the top level directory, or on-line at:
-# https://github.com/analogdevicesinc/hdl/blob/dev/LICENSE
+# This core  is distributed in the hope that it will be useful, but WITHOUT ANY
+# WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
+# A PARTICULAR PURPOSE. See the GNU General Public License for more details.
 #
-# ***************************************************************************
-# ***************************************************************************
+# You should have received a copy of the GNU General Public License version 2
+# along with this source code, and binary.  If not, see
+# <http://www.gnu.org/licenses/>.
+#
+# Commercial licenses (with commercial support) of this JESD204 core are also
+# available under terms different than the General Public License. (e.g. they
+# do not require you to accompany any image (FPGA or ASIC) using the JESD204
+# core with any corresponding source code.) For these alternate terms you must
+# purchase a license from Analog Devices Technology Licensing Office. Users
+# interested in such a license should contact [email protected] for
+# more information. This commercial license is sub-licensable (if you purchase
+# chips from Analog Devices, incorporate them into your PCB level product, and
+# purchase a JESD204 license, end users of your product will also have a
+# license to use this core in a commercial setting without releasing their
+# source code).
+#
+# In addition, we kindly ask you to acknowledge ADI in any program, application
+# or publication in which you use this JESD204 HDL core. (You are not required
+# to do so; it is up to your common sense to decide whether you want to comply
+# with this request or not.) For general publications, we suggest referencing :
+# “The design and implementation of the JESD204 HDL Core used in this project
+# is copyright © 2016-2023, Analog Devices, Inc.”
 
 package require qsys 14.0
 source ../../../scripts/adi_env.tcl
@@ -501,7 +523,7 @@ proc p_ad_ip_jesd204_tpl_dac_elab {} {
   set DMA_BPS [get_parameter_value "DMA_BITS_PER_SAMPLE"]
 
   # The DMA interface is rounded to nearest power of two bytes per sample,
-  # e.g NP=12 is padded into 16 bits 
+  # e.g NP=12 is padded into 16 bits
   set samples_per_beat_per_channel [expr ($OPB * 8 * $L / ($M * $NP))]
   set channel_bus_width [expr $samples_per_beat_per_channel*$DMA_BPS]