Random tests based Verification for Surelog-UHDM-Yosys flow

[alaindargelas]

We need to create/adapt an open-source random stimulus generator to generate/record test traces at RTL and compare with the post-synthesis simulation.
We need to apply this technique to all modules of the Ibex core to verify at the first order that the Synthesis flow performs correctly.
That has to be done before we attempt to get more sophisticated tests like the UVM based tests that come with Ibex.

We have a test harness for directed tests that employs Verilator as the simulator for unit tests, that proves that the flow works already.
The direct test approach for Ibex is not scalable, the authors of Ibex themselves voted for UVM instead.
To flush out gross errors in the Synthesis tool, we need to run pseudo randomly generated stimulus through the test harness on every modules from Ibex independently. Then on subsystem bundles.

Since random-based simulation corners itself into not interesting state space after some sequential depth,
this approach will have its limitations.
Also, special care has to be taken for clocks/resets/sets. They have to behave not as random as the rest of the signals.
A clock should look like a clock, and resets/sets should be triggered only once in a while or only at the beginning of the simulation.

Verilator is a 2 states simulator so we have to make sure Xs are removed from the picture entirely.

Surelog/UHDM itself could be used to run an analysis of the DUT to extract clocks/sets/resets to help the random generation.

[alaindargelas]

See https://github.com/alainmarcel/Surelog/issues/865
for related topic