Merge pull request #361 from adafruit/update-tinyusb-to-fix-357

update tinyusb to pr hathach/tinyusb#2412
adafruit · Jan 12, 2024 · 6de4a11 · 6de4a11
2 parents ac087e4 + 5656196
commit 6de4a11
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Showing 14 changed files with 344 additions and 338 deletions.
diff --git a/src/arduino/Adafruit_USBD_CDC.cpp b/src/arduino/Adafruit_USBD_CDC.cpp
@@ -266,7 +266,7 @@ void tud_cdc_line_state_cb(uint8_t instance, bool dtr, bool rts) {
 #else
 
 // Device stack is not enabled (probably in host mode)
-#warning "NO_USB selected. No output to Serial will occur!"
+#warning "TinyUSB Host selected. No output to Serial will occur!"
 
 uint16_t Adafruit_USBD_CDC::getInterfaceDescriptor(uint8_t itfnum, uint8_t *buf,
                                                    uint16_t bufsize) {

diff --git a/src/class/audio/audio_device.c b/src/class/audio/audio_device.c
@@ -1570,7 +1570,8 @@ uint16_t audiod_open(uint8_t rhport, tusb_desc_interface_t const * itf_desc, uin
       {
         uint8_t const *p_desc = _audiod_fct[i].p_desc;
         uint8_t const *p_desc_end = p_desc + _audiod_fct[i].desc_length - TUD_AUDIO_DESC_IAD_LEN;
-        while (p_desc < p_desc_end)
+        // Condition modified from p_desc < p_desc_end to prevent gcc>=12 strict-overflow warning
+        while (p_desc_end - p_desc > 0)
         {
           if (tu_desc_type(p_desc) == TUSB_DESC_ENDPOINT)
           {

diff --git a/src/class/cdc/cdc_host.c b/src/class/cdc/cdc_host.c
@@ -85,6 +85,7 @@ static cdch_interface_t cdch_data[CFG_TUH_CDC];
 //--------------------------------------------------------------------+
 
 //------------- ACM prototypes -------------//
+static bool acm_open(uint8_t daddr, tusb_desc_interface_t const *itf_desc, uint16_t max_len);
 static void acm_process_config(tuh_xfer_t* xfer);
 
 static bool acm_set_line_coding(cdch_interface_t* p_cdc, cdc_line_coding_t const* line_coding, tuh_xfer_cb_t complete_cb, uintptr_t user_data);
@@ -610,8 +611,6 @@ bool cdch_xfer_cb(uint8_t daddr, uint8_t ep_addr, xfer_result_t event, uint32_t
 // Enumeration
 //--------------------------------------------------------------------+
 
-static bool acm_open(uint8_t daddr, tusb_desc_interface_t const *itf_desc, uint16_t max_len);
-
 static bool open_ep_stream_pair(cdch_interface_t* p_cdc, tusb_desc_endpoint_t const *desc_ep)
 {
   for(size_t i=0; i<2; i++)
@@ -647,7 +646,7 @@ bool cdch_open(uint8_t rhport, uint8_t daddr, tusb_desc_interface_t const *itf_d
     return acm_open(daddr, itf_desc, max_len);
   }
   #if CFG_TUH_CDC_FTDI || CFG_TUH_CDC_CP210X
-  else if ( 0xff == itf_desc->bInterfaceClass )
+  else if ( TUSB_CLASS_VENDOR_SPECIFIC == itf_desc->bInterfaceClass )
   {
     uint16_t vid, pid;
     TU_VERIFY(tuh_vid_pid_get(daddr, &vid, &pid));

diff --git a/src/common/tusb_mcu.h b/src/common/tusb_mcu.h
@@ -210,6 +210,11 @@
 
   #define TUP_DCD_ENDPOINT_MAX    9
 
+#elif TU_CHECK_MCU(OPT_MCU_STM32H5)
+  #define TUP_USBIP_FSDEV
+  #define TUP_USBIP_FSDEV_STM32
+  #define TUP_DCD_ENDPOINT_MAX    8
+
 #elif TU_CHECK_MCU(OPT_MCU_STM32G4)
   // Device controller
   #define TUP_USBIP_FSDEV

diff --git a/src/common/tusb_verify.h b/src/common/tusb_verify.h
@@ -75,8 +75,8 @@
   #define _MESS_FAILED() do {} while (0)
 #endif
 
-// Halt CPU (breakpoint) when hitting error, only apply for Cortex M3, M4, M7, M33
-#if defined(__ARM_ARCH_7M__) || defined (__ARM_ARCH_7EM__) || defined(__ARM_ARCH_8M_MAIN__)
+// Halt CPU (breakpoint) when hitting error, only apply for Cortex M3, M4, M7, M33. M55
+#if defined(__ARM_ARCH_7M__) || defined (__ARM_ARCH_7EM__) || defined(__ARM_ARCH_8M_MAIN__) || defined(__ARM_ARCH_8_1M_MAIN__)
   #define TU_BREAKPOINT() do                                                                                \
   {                                                                                                         \
     volatile uint32_t* ARM_CM_DHCSR =  ((volatile uint32_t*) 0xE000EDF0UL); /* Cortex M CoreDebug->DHCSR */ \

diff --git a/src/device/dcd.h b/src/device/dcd.h
@@ -152,7 +152,7 @@ void dcd_sof_enable(uint8_t rhport, bool en);
 
 // Invoked when a control transfer's status stage is complete.
 // May help DCD to prepare for next control transfer, this API is optional.
-void dcd_edpt0_status_complete(uint8_t rhport, tusb_control_request_t const * request) TU_ATTR_WEAK;
+void dcd_edpt0_status_complete(uint8_t rhport, tusb_control_request_t const * request);
 
 // Configure endpoint's registers according to descriptor
 bool dcd_edpt_open            (uint8_t rhport, tusb_desc_endpoint_t const * desc_ep);