Skip to content

Commit

Permalink
feat: update project tt_um_MichaelBell_latch_mem from MichaelBell/tt0…
Browse files Browse the repository at this point in the history 
…6-memory

Commit: e611b46e65bb7f8a2c2e17bf946a0daf93ed04aa
Workflow: https://github.com/MichaelBell/tt06-memory/actions/runs/8757526708
  • Loading branch information
@TinyTapeoutBot @urish
TinyTapeoutBot authored and urish committed Apr 19, 2024
1 parent fe99978 commit 798f732
Show file tree
Hide file tree
Showing 7 changed files with 55,025 additions and 54,613 deletions.
6 changes: 3 additions & 3 deletions projects/tt_um_MichaelBell_latch_mem/commit_id.json
View file
Original file line number Diff line number Diff line change
@@ -1,8 +1,8 @@
{
"app": "Tiny Tapeout tt06 c74b14ac",
"app": "Tiny Tapeout tt06 7f56a586",
"repo": "https://github.com/MichaelBell/tt06-memory",
"commit": "9f50bcee1c6e8c212862c498048502afb838fa93",
"workflow_url": "https://github.com/MichaelBell/tt06-memory/actions/runs/8743762887",
"commit": "e611b46e65bb7f8a2c2e17bf946a0daf93ed04aa",
"workflow_url": "https://github.com/MichaelBell/tt06-memory/actions/runs/8757526708",
"sort_id": 1713476062118,
"openlane_version": "OpenLane eaba5192c45aa333ab45216ce1773d75d539e9b3",
"pdk_version": "open_pdks cd1748bb197f9b7af62a54507de6624e30363943"
Expand Down
2 changes: 1 addition & 1 deletion projects/tt_um_MichaelBell_latch_mem/stats/metrics.csv
View file
Original file line number Diff line number Diff line change
@@ -1,2 +1,2 @@
design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Final_Util,Peak_Memory_Usage_MB,synth_cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,pin_antenna_violations,net_antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,DecapCells,WelltapCells,DiodeCells,FillCells,NonPhysCells,TotalCells,CoreArea_um^2,power_slowest_internal_uW,power_slowest_switching_uW,power_slowest_leakage_uW,power_typical_internal_uW,power_typical_switching_uW,power_typical_leakage_uW,power_fastest_internal_uW,power_fastest_switching_uW,power_fastest_leakage_uW,critical_path_ns,suggested_clock_period,suggested_clock_frequency,CLOCK_PERIOD,FP_ASPECT_RATIO,FP_CORE_UTIL,FP_PDN_HPITCH,FP_PDN_VPITCH,GRT_ADJUSTMENT,GRT_REPAIR_ANTENNAS,MAX_FANOUT_CONSTRAINT,PL_TARGET_DENSITY,RUN_HEURISTIC_DIODE_INSERTION,STD_CELL_LIBRARY,SYNTH_STRATEGY
/work/src,tt_um_MichaelBell_latch_mem,wokwi,flow completed,0h4m31s0ms,0h4m3s0ms,135786.02172576348,0.01795472,67893.01086288174,81.99,83.23469999999999,598.13,1125,0,0,0,0,0,0,0,0,0,0,-1,-1,45456,10149,0.0,-1,-1,-1,-1,0.0,-1,-1,-1,-1,26110660.0,0.0,76.67,66.87,37.81,25.6,-1,1260,1799,155,694,0,0,0,1773,2,1,12,1,565,6,0,32,528,103,8,385,225,3,383,1219,2215,16493.3184,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,21.0,47.61904761904762,20,1,50,26.520,38.870,0.3,1,10,0.83,0,sky130_fd_sc_hd,AREA 0
/work/src,tt_um_MichaelBell_latch_mem,wokwi,flow completed,0h4m33s0ms,0h4m5s0ms,138348.02213568354,0.01795472,69174.01106784177,83.91,85.6395,602.29,1147,0,0,0,0,0,0,0,1,1,0,-1,-1,44962,10293,0.0,-1,-1,-1,-1,0.0,-1,-1,-1,-1,24800186.0,0.0,77.32,68.22,34.45,24.92,-1,1274,1816,158,700,0,0,0,1790,2,1,13,0,579,0,0,32,550,118,8,321,225,3,378,1242,2169,16493.3184,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,21.0,47.61904761904762,20,1,50,26.520,38.870,0.3,1,10,0.85,0,sky130_fd_sc_hd,AREA 0
53 changes: 28 additions & 25 deletions projects/tt_um_MichaelBell_latch_mem/stats/synthesis-stats.txt
View file
Original file line number Diff line number Diff line change
Expand Up @@ -3,43 +3,46 @@

=== tt_um_MichaelBell_latch_mem ===

Number of wires: 1085
Number of wire bits: 1120
Number of public wires: 644
Number of public wire bits: 679
Number of wires: 1107
Number of wire bits: 1142
Number of public wires: 649
Number of public wire bits: 684
Number of memories: 0
Number of memory bits: 0
Number of processes: 0
Number of cells: 1125
sky130_fd_sc_hd__a211o_2 8
sky130_fd_sc_hd__a211oi_2 1
sky130_fd_sc_hd__a221o_2 109
sky130_fd_sc_hd__a22o_2 140
sky130_fd_sc_hd__and3_2 1
Number of cells: 1147
sky130_fd_sc_hd__a2111o_2 8
sky130_fd_sc_hd__a221o_2 92
sky130_fd_sc_hd__a22o_2 156
sky130_fd_sc_hd__and2_2 2
sky130_fd_sc_hd__and4_2 1
sky130_fd_sc_hd__and4b_2 4
sky130_fd_sc_hd__and4bb_2 6
sky130_fd_sc_hd__buf_1 92
sky130_fd_sc_hd__buf_1 108
sky130_fd_sc_hd__clkbuf_4 8
sky130_fd_sc_hd__conb_1 16
sky130_fd_sc_hd__dfxtp_2 20
sky130_fd_sc_hd__dfxtp_2 25
sky130_fd_sc_hd__dlxtp_1 512
sky130_fd_sc_hd__ebufn_2 32
sky130_fd_sc_hd__inv_2 10
sky130_fd_sc_hd__nand2_2 4
sky130_fd_sc_hd__nor2_2 65
sky130_fd_sc_hd__inv_2 2
sky130_fd_sc_hd__mux2_2 14
sky130_fd_sc_hd__nand2_2 3
sky130_fd_sc_hd__nand4_2 2
sky130_fd_sc_hd__nand4b_2 2
sky130_fd_sc_hd__nor2_2 64
sky130_fd_sc_hd__nor2b_2 1
sky130_fd_sc_hd__nor4_2 1
sky130_fd_sc_hd__nor4b_2 3
sky130_fd_sc_hd__o211ai_2 1
sky130_fd_sc_hd__o221a_2 2
sky130_fd_sc_hd__o22a_2 9
sky130_fd_sc_hd__or2_2 28
sky130_fd_sc_hd__or3_2 29
sky130_fd_sc_hd__or3b_2 1
sky130_fd_sc_hd__or4_2 21
sky130_fd_sc_hd__xnor2_2 1
sky130_fd_sc_hd__nor4b_2 4
sky130_fd_sc_hd__o22a_2 8
sky130_fd_sc_hd__or2_2 19
sky130_fd_sc_hd__or2b_2 2
sky130_fd_sc_hd__or3_2 26
sky130_fd_sc_hd__or3b_2 4
sky130_fd_sc_hd__or4_2 16
sky130_fd_sc_hd__or4b_2 4
sky130_fd_sc_hd__or4bb_2 5

Area for cell type \sky130_fd_sc_hd__clkbuf_4 is unknown!

Chip area for module '\tt_um_MichaelBell_latch_mem': 12991.209600
Chip area for module '\tt_um_MichaelBell_latch_mem': 13297.753600

Binary file modified projects/tt_um_MichaelBell_latch_mem/tt_um_MichaelBell_latch_mem.gds
View file
Binary file not shown.
112 changes: 67 additions & 45 deletions projects/tt_um_MichaelBell_latch_mem/tt_um_MichaelBell_latch_mem.lef
View file
Original file line number Diff line number Diff line change
Expand Up @@ -67,6 +67,7 @@ MACRO tt_um_MichaelBell_latch_mem
PIN rst_n
DIRECTION INPUT ;
USE SIGNAL ;
ANTENNAGATEAREA 0.196500 ;
PORT
LAYER met4 ;
RECT 151.190 110.520 151.490 111.520 ;
Expand Down Expand Up @@ -416,56 +417,77 @@ MACRO tt_um_MichaelBell_latch_mem
END
END uo_out[7]
OBS
LAYER nwell ;
RECT 2.570 107.385 158.430 108.990 ;
RECT 2.570 101.945 158.430 104.775 ;
RECT 2.570 96.505 158.430 99.335 ;
RECT 2.570 91.065 158.430 93.895 ;
RECT 2.570 85.625 158.430 88.455 ;
RECT 2.570 80.185 158.430 83.015 ;
RECT 2.570 74.745 158.430 77.575 ;
RECT 2.570 69.305 158.430 72.135 ;
RECT 2.570 63.865 158.430 66.695 ;
RECT 2.570 58.425 158.430 61.255 ;
RECT 2.570 52.985 158.430 55.815 ;
RECT 2.570 47.545 158.430 50.375 ;
RECT 2.570 42.105 158.430 44.935 ;
RECT 2.570 36.665 158.430 39.495 ;
RECT 2.570 31.225 158.430 34.055 ;
RECT 2.570 25.785 158.430 28.615 ;
RECT 2.570 20.345 158.430 23.175 ;
RECT 2.570 14.905 158.430 17.735 ;
RECT 2.570 9.465 158.430 12.295 ;
RECT 2.570 4.025 158.430 6.855 ;
LAYER li1 ;
RECT 2.760 2.635 158.240 108.885 ;
LAYER met1 ;
RECT 2.460 0.720 160.010 111.140 ;
RECT 2.760 0.720 160.470 111.480 ;
LAYER met2 ;
RECT 4.230 0.690 159.980 111.365 ;
RECT 4.230 0.690 160.440 111.510 ;
LAYER met3 ;
RECT 3.950 2.555 159.030 111.345 ;
LAYER met4 ;
RECT 4.690 110.120 7.270 111.345 ;
RECT 8.370 110.120 10.950 111.345 ;
RECT 12.050 110.120 14.630 111.345 ;
RECT 15.730 110.120 18.310 111.345 ;
RECT 19.410 110.120 21.990 111.345 ;
RECT 23.090 110.120 25.670 111.345 ;
RECT 26.770 110.120 29.350 111.345 ;
RECT 30.450 110.120 33.030 111.345 ;
RECT 34.130 110.120 36.710 111.345 ;
RECT 37.810 110.120 40.390 111.345 ;
RECT 41.490 110.120 44.070 111.345 ;
RECT 45.170 110.120 47.750 111.345 ;
RECT 48.850 110.120 51.430 111.345 ;
RECT 52.530 110.120 55.110 111.345 ;
RECT 56.210 110.120 58.790 111.345 ;
RECT 59.890 110.120 62.470 111.345 ;
RECT 63.570 110.120 66.150 111.345 ;
RECT 67.250 110.120 69.830 111.345 ;
RECT 70.930 110.120 73.510 111.345 ;
RECT 74.610 110.120 77.190 111.345 ;
RECT 78.290 110.120 80.870 111.345 ;
RECT 81.970 110.120 84.550 111.345 ;
RECT 85.650 110.120 88.230 111.345 ;
RECT 89.330 110.120 91.910 111.345 ;
RECT 93.010 110.120 95.590 111.345 ;
RECT 96.690 110.120 99.270 111.345 ;
RECT 100.370 110.120 102.950 111.345 ;
RECT 104.050 110.120 106.630 111.345 ;
RECT 107.730 110.120 110.310 111.345 ;
RECT 111.410 110.120 113.990 111.345 ;
RECT 115.090 110.120 117.670 111.345 ;
RECT 118.770 110.120 121.350 111.345 ;
RECT 122.450 110.120 125.030 111.345 ;
RECT 126.130 110.120 128.710 111.345 ;
RECT 129.810 110.120 132.390 111.345 ;
RECT 133.490 110.120 136.070 111.345 ;
RECT 137.170 110.120 139.750 111.345 ;
RECT 140.850 110.120 143.430 111.345 ;
RECT 144.530 110.120 147.110 111.345 ;
RECT 148.210 110.120 150.790 111.345 ;
RECT 151.890 110.120 154.470 111.345 ;
RECT 3.950 2.555 159.030 110.665 ;
LAYER met4 ;
RECT 4.690 110.120 7.270 111.170 ;
RECT 8.370 110.120 10.950 111.170 ;
RECT 12.050 110.120 14.630 111.170 ;
RECT 15.730 110.120 18.310 111.170 ;
RECT 19.410 110.120 21.990 111.170 ;
RECT 23.090 110.120 25.670 111.170 ;
RECT 26.770 110.120 29.350 111.170 ;
RECT 30.450 110.120 33.030 111.170 ;
RECT 34.130 110.120 36.710 111.170 ;
RECT 37.810 110.120 40.390 111.170 ;
RECT 41.490 110.120 44.070 111.170 ;
RECT 45.170 110.120 47.750 111.170 ;
RECT 48.850 110.120 51.430 111.170 ;
RECT 52.530 110.120 55.110 111.170 ;
RECT 56.210 110.120 58.790 111.170 ;
RECT 59.890 110.120 62.470 111.170 ;
RECT 63.570 110.120 66.150 111.170 ;
RECT 67.250 110.120 69.830 111.170 ;
RECT 70.930 110.120 73.510 111.170 ;
RECT 74.610 110.120 77.190 111.170 ;
RECT 78.290 110.120 80.870 111.170 ;
RECT 81.970 110.120 84.550 111.170 ;
RECT 85.650 110.120 88.230 111.170 ;
RECT 89.330 110.120 91.910 111.170 ;
RECT 93.010 110.120 95.590 111.170 ;
RECT 96.690 110.120 99.270 111.170 ;
RECT 100.370 110.120 102.950 111.170 ;
RECT 104.050 110.120 106.630 111.170 ;
RECT 107.730 110.120 110.310 111.170 ;
RECT 111.410 110.120 113.990 111.170 ;
RECT 115.090 110.120 117.670 111.170 ;
RECT 118.770 110.120 121.350 111.170 ;
RECT 122.450 110.120 125.030 111.170 ;
RECT 126.130 110.120 128.710 111.170 ;
RECT 129.810 110.120 132.390 111.170 ;
RECT 133.490 110.120 136.070 111.170 ;
RECT 137.170 110.120 139.750 111.170 ;
RECT 140.850 110.120 143.430 111.170 ;
RECT 144.530 110.120 147.110 111.170 ;
RECT 148.210 110.120 150.790 111.170 ;
RECT 151.890 110.120 154.470 111.170 ;
RECT 3.975 109.440 155.185 110.120 ;
RECT 3.975 6.295 20.995 109.440 ;
RECT 23.395 6.295 40.430 109.440 ;
Expand Down
Loading

0 comments on commit 798f732

Please sign in to comment.