feat: update project tt_um_spi_pwm_djuara from djuara-rbz/tt_spi_pwm

Commit: 7f7de099f73b56b5f82ceffa6a6b2cef65e99a4d
Workflow: https://github.com/djuara-rbz/tt_spi_pwm/actions/runs/8295333665

projects/tt_um_spi_pwm_djuara/LICENSE

@@ -0,0 +1,201 @@
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projects/tt_um_spi_pwm_djuara/commit_id.json

@@ -0,0 +1,9 @@
+{
+  "app": "Tiny Tapeout tt06 51bb1d0b",
+  "repo": "https://github.com/djuara-rbz/tt_spi_pwm",
+  "commit": "7f7de099f73b56b5f82ceffa6a6b2cef65e99a4d",
+  "workflow_url": "https://github.com/djuara-rbz/tt_spi_pwm/actions/runs/8295333665",
+  "sort_id": 1710577973646,
+  "openlane_version": "OpenLane f691c8c0712ca6c6645e3fd548985b3cbcf08c78",
+  "pdk_version": "open_pdks e0f692f46654d6c7c99fc70a0c94a080dab53571"
+}

projects/tt_um_spi_pwm_djuara/docs/info.md

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+<!---
+
+This file is used to generate your project datasheet. Please fill in the information below and delete any unused
+sections.
+
+You can also include images in this folder and reference them in the markdown. Each image must be less than
+512 kb in size, and the combined size of all images must be less than 1 MB.
+-->
+
+## How it works
+
+This design is a test of SPI Slave. It has X device registers, register 0x00 is ID and is read only.
+Other registers can be written and read. 
+
+To write a register, 16 bits must be written. 
+
+Bit 15 (MSB, first sent) is the R/W bit, for writes, must be 0
+Bit 14 to 8 is address
+Bit 7 to 0 is data to be written
+
+To read a register, 24 bits must be sent
+
+Bit 23 (MSB, first sent) is the R/W bit, for reads, must be 1
+Bit 22 to 16 is address
+Bit 15 to 8 is dummy bits
+Bit 7 to 0 is data read in MISO line
+
+## How to test
+
+In order to test reads, you can read the ID register (0x00) and the byte received should be 0x96.
+
+In order to test writes, you can write a register different than ID register, and then read it back an check
+you read the value previously written.
+
+## External hardware
+
+Some devices to peform SPI transactions

projects/tt_um_spi_pwm_djuara/info.yaml

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+# Tiny Tapeout project information
+project:
+  title:        "spi_test"      # Project title
+  author:       "djuara"      # Your name
+  discord:      ""      # Your discord username, for communication and automatically assigning you a Tapeout role (optional)
+  description:  "This is a PWM generator, spi controlled (2 different interfaces, just for testing)"      # One line description of what your project does
+  language:     "Verilog" # other examples include SystemVerilog, Amaranth, VHDL, etc
+  clock_hz:     0       # Clock frequency in Hz (or 0 if not applicable)
+
+  # How many tiles your design occupies? A single tile is about 167x108 uM.
+  tiles: "1x1"          # Valid values: 1x1, 1x2, 2x2, 3x2, 4x2, 6x2 or 8x2
+
+  # Your top module name must start with "tt_um_". Make it unique by including your github username:
+  top_module:  "tt_um_spi_pwm_djuara"
+
+  # List your project's source files here. Source files must be in ./src and you must list each source file separately, one per line:
+  source_files:        
+    - "project.v"
+    - "edge_detector.v"
+    - "spi_own_clock.v"
+    - "spi_sampled.v"
+    - "pwm.v"
+
+# The pinout of your project. Leave unused pins blank. DO NOT delete or add any pins.
+pinout:
+  # Inputs
+  ui[0]: "clk_sclk"
+  ui[1]: "clk_mosi"
+  ui[2]: "clk_cs"
+  ui[3]: "sampled_sclk"
+  ui[4]: "sampled_mosi"
+  ui[5]: "sampled_cs"
+  ui[6]: ""
+  ui[7]: ""
+
+  # Outputs
+  uo[0]: "clk_miso"
+  uo[1]: "sampled_miso"
+  uo[2]: "pwm"
+  uo[3]: ""
+  uo[4]: ""
+  uo[5]: ""
+  uo[6]: ""
+  uo[7]: ""
+
+  # Bidirectional pins
+  uio[0]: ""
+  uio[1]: ""
+  uio[2]: ""
+  uio[3]: ""
+  uio[4]: ""
+  uio[5]: ""
+  uio[6]: ""
+  uio[7]: ""
+
+# Do not change!
+yaml_version: 6

projects/tt_um_spi_pwm_djuara/stats/metrics.csv

@@ -0,0 +1,2 @@
+design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Final_Util,Peak_Memory_Usage_MB,synth_cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,pin_antenna_violations,net_antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,DecapCells,WelltapCells,DiodeCells,FillCells,NonPhysCells,TotalCells,CoreArea_um^2,power_slowest_internal_uW,power_slowest_switching_uW,power_slowest_leakage_uW,power_typical_internal_uW,power_typical_switching_uW,power_typical_leakage_uW,power_fastest_internal_uW,power_fastest_switching_uW,power_fastest_leakage_uW,critical_path_ns,suggested_clock_period,suggested_clock_frequency,CLOCK_PERIOD,FP_ASPECT_RATIO,FP_CORE_UTIL,FP_PDN_HPITCH,FP_PDN_VPITCH,GRT_ADJUSTMENT,GRT_REPAIR_ANTENNAS,MAX_FANOUT_CONSTRAINT,PL_TARGET_DENSITY,RUN_HEURISTIC_DIODE_INSERTION,STD_CELL_LIBRARY,SYNTH_STRATEGY
+/work/src,tt_um_spi_pwm_djuara,wokwi,flow completed,0h4m37s0ms,0h4m9s0ms,131218.97751677554,0.01795472,65609.48875838777,74.4,79.19890000000001,566.48,1115,0,0,0,0,0,0,0,0,0,0,-1,-1,29354,8640,0.0,-1,-1,-1,-1,0.0,-1,-1,-1,-1,19518531.0,0.0,60.33,45.09,15.22,4.71,-1,1174,1560,80,453,0,0,0,1295,101,8,36,26,234,67,37,94,183,231,11,532,225,5,416,1178,2356,16493.3184,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,21.0,47.61904761904762,20,1,50,26.520,38.870,0.3,1,10,0.75,0,sky130_fd_sc_hd,AREA 0

projects/tt_um_spi_pwm_djuara/stats/synthesis-stats.txt

@@ -0,0 +1,77 @@
+
+66. Printing statistics.
+
+=== tt_um_spi_pwm_djuara ===
+
+   Number of wires:               1099
+   Number of wire bits:           1134
+   Number of public wires:         186
+   Number of public wire bits:     221
+   Number of memories:               0
+   Number of memory bits:            0
+   Number of processes:              0
+   Number of cells:               1115
+     sky130_fd_sc_hd__a2111o_2       4
+     sky130_fd_sc_hd__a211o_2       25
+     sky130_fd_sc_hd__a211oi_2       1
+     sky130_fd_sc_hd__a21bo_2        4
+     sky130_fd_sc_hd__a21boi_2       2
+     sky130_fd_sc_hd__a21o_2        22
+     sky130_fd_sc_hd__a21oi_2       11
+     sky130_fd_sc_hd__a221o_2       37
+     sky130_fd_sc_hd__a221oi_2       2
+     sky130_fd_sc_hd__a22o_2        50
+     sky130_fd_sc_hd__a22oi_2        4
+     sky130_fd_sc_hd__a2bb2o_2       7
+     sky130_fd_sc_hd__a311o_2        1
+     sky130_fd_sc_hd__a31o_2         8
+     sky130_fd_sc_hd__a32o_2         3
+     sky130_fd_sc_hd__a41o_2         3
+     sky130_fd_sc_hd__and2_2        15
+     sky130_fd_sc_hd__and2b_2       22
+     sky130_fd_sc_hd__and3_2        24
+     sky130_fd_sc_hd__and3b_2       30
+     sky130_fd_sc_hd__and4_2        11
+     sky130_fd_sc_hd__and4b_2        4
+     sky130_fd_sc_hd__and4bb_2       7
+     sky130_fd_sc_hd__buf_1        191
+     sky130_fd_sc_hd__buf_2          3
+     sky130_fd_sc_hd__conb_1        21
+     sky130_fd_sc_hd__dfrtp_2      151
+     sky130_fd_sc_hd__dfstp_2       17
+     sky130_fd_sc_hd__dfxtp_2        8
+     sky130_fd_sc_hd__inv_2         73
+     sky130_fd_sc_hd__mux2_2       112
+     sky130_fd_sc_hd__mux4_2         2
+     sky130_fd_sc_hd__nand2_2       34
+     sky130_fd_sc_hd__nor2_2        62
+     sky130_fd_sc_hd__nor3_2         1
+     sky130_fd_sc_hd__nor3b_2        2
+     sky130_fd_sc_hd__nor4b_2        1
+     sky130_fd_sc_hd__o2111a_2       3
+     sky130_fd_sc_hd__o211a_2        6
+     sky130_fd_sc_hd__o211ai_2       1
+     sky130_fd_sc_hd__o21a_2         8
+     sky130_fd_sc_hd__o21ai_2        6
+     sky130_fd_sc_hd__o21ba_2        5
+     sky130_fd_sc_hd__o21bai_2       2
+     sky130_fd_sc_hd__o221a_2       16
+     sky130_fd_sc_hd__o221ai_2       3
+     sky130_fd_sc_hd__o22a_2         8
+     sky130_fd_sc_hd__o22ai_2        1
+     sky130_fd_sc_hd__o2bb2a_2       1
+     sky130_fd_sc_hd__o311a_2        1
+     sky130_fd_sc_hd__o31a_2         1
+     sky130_fd_sc_hd__o32a_2         1
+     sky130_fd_sc_hd__or2_2         33
+     sky130_fd_sc_hd__or2b_2        19
+     sky130_fd_sc_hd__or3_2          7
+     sky130_fd_sc_hd__or3b_2         3
+     sky130_fd_sc_hd__or4_2          7
+     sky130_fd_sc_hd__or4b_2         1
+     sky130_fd_sc_hd__or4bb_2        1
+     sky130_fd_sc_hd__xnor2_2        2
+     sky130_fd_sc_hd__xor2_2         4
+
+   Chip area for module '\tt_um_spi_pwm_djuara': 11843.859200
+