Better decode instructions

source/VexiiRiscv/Decode/index.rst

@@ -1,14 +1,13 @@
 Decode
 ======
 
-A few plugins operate in the fetch stage :
-
-- DecodePipelinePlugin
-- AlignerPlugin
-- DecoderPlugin
-- DispatchPlugin
-- DecodePredictionPlugin
+The Decode pipeline has a few tasks :
 
+- Translating the stream of fetched words into individual instructions
+- Figuring out instructions needs, mostly "does it need to read/write the register file ?"
+- Checking the execution lanes compatibility with incoming instruction. For instance, a memory load instruction can only be scheduled to the execute lane with the LSU
+- Ensuring that all branch prediction done in the fetch pipeline were done on real branch instructions.
+- Feed the execution lanes with instructions
 
 DecodePipelinePlugin
 --------------------

source/VexiiRiscv/Introduction/index.rst

@@ -91,6 +91,7 @@ Here is a few acronyms commonly used across the documentation :
 - **CPU** : Central Processing Unit
 - **HART** : Hardware Thread. One CPU core can for instance implement multiple HART, meaning that it will execute multiple threads concurently.
   **For** instance, most modern PC CPUs implement 2 Hardware Thread per CPU core (this feature is called hyper-threading)
+- **RF** : Register file
 - **ALU** : Arithmetic Logical Unit
 - **FPU** : Floating Point Unit
 - **LSU** : Load Store Unit