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Fix CsrPlugin FPU access
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Dolu1990 committed Sep 20, 2024
1 parent 9dcf5c3 commit 7fac668
Showing 1 changed file with 1 addition and 1 deletion.
2 changes: 1 addition & 1 deletion src/main/scala/vexriscv/plugin/CsrPlugin.scala
Original file line number Diff line number Diff line change
Expand Up @@ -784,7 +784,7 @@ class CsrPlugin(val config: CsrPluginConfig) extends Plugin[VexRiscv] with Excep
buffer.ready := injectionPort.fire
val fpu = withDebugFpuAccess generate new Area {
val access = service(classOf[FpuPlugin]).access
access.start := buffer.valid && buffer.op === DebugDmToHartOp.REG_READ || buffer.op === DebugDmToHartOp.REG_WRITE
access.start := buffer.valid && (buffer.op === DebugDmToHartOp.REG_READ || buffer.op === DebugDmToHartOp.REG_WRITE)
access.regId := buffer.address
access.write := buffer.op === DebugDmToHartOp.REG_WRITE
access.writeData := dataCsrw.value.take(2).asBits
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