Merge branch 'master' into tensor-core

SparseLinearAlgebra · Oct 4, 2024 · faa3b9a · faa3b9a
2 parents 119805a + 847562b
commit faa3b9a
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diff --git a/hw/rtl/Vortex_hbm.sv b/hw/rtl/Vortex_hbm.sv
diff --git a/hw/rtl/cache/VX_cache_bypass.sv b/hw/rtl/cache/VX_cache_bypass.sv
@@ -247,9 +247,7 @@ module VX_cache_bypass #(
         assign is_mem_rsp_nc = 1'b0;
     end
 
-    `IGNORE_UNUSED_BEGIN
     wire [(MEM_TAG_OUT_WIDTH - NC_ENABLE)-1:0] mem_rsp_tag_id_nc;
-    `IGNORE_UNUSED_END
 
     VX_bits_remove #(
         .N   (MEM_TAG_OUT_WIDTH),