Merge branch 'main' of https://github.com/nanoframework/nf-interpreter …

…into orgpal-mesh
OrgPal · Apr 25, 2024 · 2561eac · 2561eac
2 parents 1ce2345 + 453bf3d
commit 2561eac
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Showing 3 changed files with 18 additions and 7 deletions.
diff --git a/targets/ChibiOS/_common/WireProtocol_ReceiverThread.c b/targets/ChibiOS/_common/WireProtocol_ReceiverThread.c
@@ -19,8 +19,6 @@ __attribute__((noreturn)) void ReceiverThread(void const *argument)
 {
     (void)argument;
 
-    osDelay(500);
-
     WP_Message_PrepareReception();
 
     // loop until thread receives a request to terminate
@@ -53,7 +51,12 @@ __attribute__((noreturn)) void ReceiverThread(void const *argument)
     // this function never returns
 }
 
+__nfweak void WP_Message_PrepareReception_Target()
+{
+    // empty on purpose, to be implemented by target if needed
+}
+
 void WP_Message_PrepareReception_Platform()
 {
-    // empty on purpose, nothing to configure
+    WP_Message_PrepareReception_Target();
 }
diff --git a/targets/ESP32/_common/Target_Windows_Storage.c b/targets/ESP32/_common/Target_Windows_Storage.c
@@ -160,8 +160,10 @@ bool Storage_MountSpi(int spiBus, uint32_t csPin, int driveIndex)
 
     sdmmc_host_t host = SDSPI_HOST_DEFAULT();
 #if defined(CONFIG_IDF_TARGET_ESP32C3) || defined(CONFIG_IDF_TARGET_ESP32S3)
-    host.slot = spiBus;
+    // First available bus on ESP32_C3/S3 is SPI2_HOST
+    host.slot = spiBus + SPI2_HOST;
 #else
+    // First available bus on ESP32 is HSPI_HOST(1)
     host.slot = spiBus + HSPI_HOST;
 #endif
 

diff --git a/targets/ESP32/_nanoCLR/System.Device.Spi/cpu_spi.cpp b/targets/ESP32/_nanoCLR/System.Device.Spi/cpu_spi.cpp
@@ -189,8 +189,10 @@ bool CPU_SPI_Initialize(uint8_t busIndex, const SPI_DEVICE_CONFIGURATION &spiDev
     if (ret != ESP_OK)
     {
 #if defined(CONFIG_IDF_TARGET_ESP32C3) || defined(CONFIG_IDF_TARGET_ESP32S3)
-        ESP_LOGE(TAG, "Unable to init SPI bus %d esp_err %d", busIndex, ret);
+        // First available bus on ESP32_C3/S3 is SPI2_HOST
+        ESP_LOGE(TAG, "Unable to init SPI bus %d esp_err %d", busIndex + SPI2_HOST, ret);
 #else
+        // First available bus on ESP32 is HSPI_HOST(1)
         ESP_LOGE(TAG, "Unable to init SPI bus %d esp_err %d", busIndex + HSPI_HOST, ret);
 #endif
         return false;
@@ -208,16 +210,20 @@ bool CPU_SPI_Initialize(uint8_t busIndex, const SPI_DEVICE_CONFIGURATION &spiDev
 bool CPU_SPI_Uninitialize(uint8_t busIndex)
 {
 #if defined(CONFIG_IDF_TARGET_ESP32C3) || defined(CONFIG_IDF_TARGET_ESP32S3)
-    esp_err_t ret = spi_bus_free((spi_host_device_t)(busIndex));
+    // First available bus on ESP32_C3/S3 is SPI2_HOST
+    esp_err_t ret = spi_bus_free((spi_host_device_t)(busIndex + SPI2_HOST));
 #else
+    // First available bus on ESP32 is HSPI_HOST(1)
     esp_err_t ret = spi_bus_free((spi_host_device_t)(busIndex + HSPI_HOST));
 #endif
 
     if (ret != ESP_OK)
     {
 #if defined(CONFIG_IDF_TARGET_ESP32C3) || defined(CONFIG_IDF_TARGET_ESP32S3)
-        ESP_LOGE(TAG, "spi_bus_free bus %d esp_err %d", busIndex, ret);
+        // First available bus on ESP32_C3/S3 is SPI2_HOST
+        ESP_LOGE(TAG, "spi_bus_free bus %d esp_err %d", busIndex + SPI2_HOST, ret);
 #else
+        // First available bus on ESP32 is HSPI_HOST(1)
         ESP_LOGE(TAG, "spi_bus_free bus %d esp_err %d", busIndex + HSPI_HOST, ret);
 #endif