Merge branch 'OP-TEE:master' into k3/tisci-locks

.github/workflows/ci.yml

@@ -356,6 +356,45 @@ jobs:
           make -j$(nproc) check CFG_PAN=y
           make -j$(nproc) check CFG_WITH_PAGER=y
 
+  QEMUv8_clang_check:
+    name: make check (QEMUv8, Clang)
+    runs-on: ubuntu-latest
+    container: jforissier/optee_os_ci:qemu_check
+    steps:
+      - name: Remove /__t/*
+        run: rm -rf /__t/*
+      - name: Restore build cache
+        uses: actions/cache@v4
+        with:
+          path: /github/home/.cache/ccache
+          key: qemuv8_check-cache-${{ github.sha }}
+          restore-keys: |
+            qemuv8_check-cache-
+      - name: Checkout
+        uses: actions/checkout@v4
+      - name: Update Git config
+        run: git config --global --add safe.directory ${GITHUB_WORKSPACE}
+      - shell: bash
+        run: |
+          # make check task
+          set -e -v
+          export LC_ALL=C
+          export BR2_CCACHE_DIR=/github/home/.cache/ccache
+          export FORCE_UNSAFE_CONFIGURE=1 # Prevent Buildroot error when building as root
+          export CFG_TEE_CORE_LOG_LEVEL=0
+          export CFG_ATTESTATION_PTA=y
+          export CFG_ATTESTATION_PTA_KEY_SIZE=1024
+          export COMPILER=clang
+          OPTEE_OS_TO_TEST=$(pwd)
+          cd ..
+          TOP=$(pwd)/optee_repo_qemu_v8
+          /root/get_optee.sh qemu_v8 ${TOP}
+          mv ${TOP}/optee_os ${TOP}/optee_os_old
+          ln -s ${OPTEE_OS_TO_TEST} ${TOP}/optee_os
+          cd ${TOP}/build
+
+          make -j$(nproc) check
+
   QEMUv8_Xen_check:
     name: make check (QEMUv8, Xen)
     runs-on: ubuntu-latest

CHANGELOG.md

@@ -1,3 +1,33 @@
+# OP-TEE - version 4.4.0 (2024-10-18)
+
+- Links to the release pages, commits and pull requests merged into this release for:
+  - OP-TEE/optee_os: [release page][OP_TEE_optee_os_release_4_4_0], [commits][OP_TEE_optee_os_commits_4_4_0] and [pull requests][OP_TEE_optee_os_pr_4_4_0]
+  - OP-TEE/optee_client: [release page][OP_TEE_optee_client_release_4_4_0], [commits][OP_TEE_optee_client_commits_4_4_0] and [pull requests][OP_TEE_optee_client_pr_4_4_0]
+  - OP-TEE/optee_test: [release page][OP_TEE_optee_test_release_4_4_0], [commits][OP_TEE_optee_test_commits_4_4_0] and [pull requests][OP_TEE_optee_test_pr_4_4_0]
+  - OP-TEE/build: [release page][OP_TEE_build_release_4_4_0], [commits][OP_TEE_build_commits_4_4_0] and [pull requests][OP_TEE_build_pr_4_4_0]
+  - linaro-swg/optee_examples: [release page][linaro_swg_optee_examples_release_4_4_0], [commits][linaro_swg_optee_examples_commits_4_4_0] and [pull requests][linaro_swg_optee_examples_pr_4_4_0]
+
+
+[OP_TEE_optee_os_release_4_4_0]: https://github.com/OP-TEE/optee_os/releases/tag/4.4.0
+[OP_TEE_optee_os_commits_4_4_0]: https://github.com/OP-TEE/optee_os/compare/4.3.0...4.4.0
+[OP_TEE_optee_os_pr_4_4_0]: https://github.com/OP-TEE/optee_os/pulls?q=is%3Apr+is%3Amerged+base%3Amaster+merged%3A2024-07-12..2024-10-18
+
+[OP_TEE_optee_client_release_4_4_0]: https://github.com/OP-TEE/optee_client/releases/tag/4.4.0
+[OP_TEE_optee_client_commits_4_4_0]: https://github.com/OP-TEE/optee_client/compare/4.3.0...4.4.0
+[OP_TEE_optee_client_pr_4_4_0]: https://github.com/OP-TEE/optee_client/pulls?q=is%3Apr+is%3Amerged+base%3Amaster+merged%3A2024-07-12..2024-10-18
+
+[OP_TEE_optee_test_release_4_4_0]: https://github.com/OP-TEE/optee_test/releases/tag/4.4.0
+[OP_TEE_optee_test_commits_4_4_0]: https://github.com/OP-TEE/optee_test/compare/4.3.0...4.4.0
+[OP_TEE_optee_test_pr_4_4_0]: https://github.com/OP-TEE/optee_test/pulls?q=is%3Apr+is%3Amerged+base%3Amaster+merged%3A2024-07-12..2024-10-18
+
+[OP_TEE_build_release_4_4_0]: https://github.com/OP-TEE/build/releases/tag/4.4.0
+[OP_TEE_build_commits_4_4_0]: https://github.com/OP-TEE/build/compare/4.3.0...4.4.0
+[OP_TEE_build_pr_4_4_0]: https://github.com/OP-TEE/build/pulls?q=is%3Apr+is%3Amerged+base%3Amaster+merged%3A2024-07-12..2024-10-18
+
+[linaro_swg_optee_examples_release_4_4_0]: https://github.com/linaro-swg/optee_examples/releases/tag/4.4.0
+[linaro_swg_optee_examples_commits_4_4_0]: https://github.com/linaro-swg/optee_examples/compare/4.3.0...4.4.0
+[linaro_swg_optee_examples_pr_4_4_0]: https://github.com/linaro-swg/optee_examples/pulls?q=is%3Apr+is%3Amerged+base%3Amaster+merged%3A2024-07-12..2024-10-18
+
 # OP-TEE - version 4.3.0 (2024-07-12)
 
 - Links to the release pages, commits and pull requests merged into this release for:

core/arch/arm/cpu/cortex-armv9.mk

@@ -0,0 +1,14 @@
+$(call force,CFG_HWSUPP_MEM_PERM_WXN,y)
+$(call force,CFG_HWSUPP_MEM_PERM_PXN,y)
+$(call force,CFG_ENABLE_SCTLR_RR,n)
+$(call force,CFG_ENABLE_SCTLR_Z,n)
+
+arm32-platform-cflags 	+= -mcpu=$(arm32-platform-cpuarch)
+arm32-platform-aflags 	+= -mcpu=$(arm32-platform-cpuarch)
+arm32-platform-cxxflags	+= -mcpu=$(arm32-platform-cpuarch)
+
+arm64-platform-cflags 	+= -mcpu=$(arm64-platform-cpuarch)
+arm64-platform-aflags 	+= -mcpu=$(arm64-platform-cpuarch)
+arm64-platform-cxxflags	+= -mcpu=$(arm64-platform-cpuarch)
+
+platform-flavor-armv9 	:= 1

core/arch/arm/cpu/neoverse-v2.mk

@@ -0,0 +1,4 @@
+arm32-platform-cpuarch 	:= neoverse-v2
+arm64-platform-cpuarch 	:= neoverse-v2
+
+include core/arch/arm/cpu/cortex-armv9.mk

core/arch/arm/plat-imx/conf.mk

@@ -262,7 +262,7 @@ $(call force,CFG_IMX_OCOTP,n)
 $(call force,CFG_TZC380,n)
 $(call force,CFG_NXP_CAAM,n)
 CFG_IMX_MU ?= y
-CFG_IMX_ELE ?= y
+CFG_IMX_ELE ?= n
 else
 $(error Unsupported PLATFORM_FLAVOR "$(PLATFORM_FLAVOR)")
 endif
@@ -542,6 +542,7 @@ CFG_SHMEM_START ?= ($(CFG_TZDRAM_START) + $(CFG_TZDRAM_SIZE))
 
 # Enable embedded tests by default
 CFG_ENABLE_EMBEDDED_TESTS ?= y
+CFG_ATTESTATION_PTA ?= y
 
 # Set default heap size for imx platforms to 128k
 CFG_CORE_HEAP_SIZE ?= 131072
@@ -556,6 +557,7 @@ endif
 CFG_IMX_OCOTP ?= y
 CFG_IMX_DIGPROG ?= y
 CFG_PKCS11_TA ?= y
+CFG_CORE_HUK_SUBKEY_COMPAT_USE_OTP_DIE_ID ?= y
 
 # Almost all platforms include CAAM HW Modules, except the
 # ones forced to be disabled

core/arch/arm/plat-rd1ae/conf.mk

@@ -0,0 +1,27 @@
+# RD-1 AE is based on Neoverse V3AE CPU, but there is
+# no compiler support for it yet. Use Neoverse V2 until
+# it becomes available.
+include core/arch/arm/cpu/neoverse-v2.mk
+
+# ARM debugger needs this
+platform-cflags-debug-info = -gdwarf-4
+platform-aflags-debug-info = -gdwarf-4
+
+$(call force,CFG_ARM64_core,y)
+
+$(call force,CFG_ARM_GICV3,y)
+
+CFG_CORE_SEL1_SPMC      ?= y
+CFG_WITH_ARM_TRUSTED_FW	?= y
+CFG_CORE_RESERVED_SHM   ?= n
+
+$(call force,CFG_GIC,y)
+$(call force,CFG_PL011,y)
+$(call force,CFG_SECURE_TIME_SOURCE_CNTPCT,y)
+$(call force,CFG_CORE_ARM64_PA_BITS,42)
+$(call force,CFG_TEE_CORE_NB_CORE,16)
+
+CFG_CORE_HEAP_SIZE ?= 0x32000
+
+CFG_TZDRAM_START ?= 0xFFC00000
+CFG_TZDRAM_SIZE  ?= 0x00400000

core/arch/arm/plat-rd1ae/main.c

@@ -0,0 +1,39 @@
+// SPDX-License-Identifier: BSD-2-Clause
+/*
+ * Copyright (c) 2024, Arm Limited
+ */
+
+#include <console.h>
+#include <drivers/gic.h>
+#include <drivers/pl011.h>
+#include <kernel/boot.h>
+#include <mm/core_mmu.h>
+#include <platform_config.h>
+#include <stdint.h>
+#include <trace.h>
+
+static struct pl011_data console_data __nex_bss;
+
+register_ddr(DRAM0_BASE, DRAM0_SIZE);
+register_ddr(DRAM1_BASE, DRAM1_SIZE);
+
+register_phys_mem_pgdir(MEM_AREA_IO_SEC, CONSOLE_UART_BASE, PL011_REG_SIZE);
+register_phys_mem_pgdir(MEM_AREA_IO_SEC, GICD_BASE, GIC_DIST_REG_SIZE);
+register_phys_mem_pgdir(MEM_AREA_IO_SEC, GICC_BASE, GIC_CPU_REG_SIZE);
+
+void boot_primary_init_intc(void)
+{
+	gic_init(GICC_BASE, GICD_BASE);
+}
+
+void boot_secondary_init_intc(void)
+{
+	gic_init_per_cpu();
+}
+
+void plat_console_init(void)
+{
+	pl011_init(&console_data, CONSOLE_UART_BASE, CONSOLE_UART_CLK_IN_HZ,
+		   CONSOLE_BAUDRATE);
+	register_serial_console(&console_data.chip);
+}

core/arch/arm/plat-rd1ae/platform_config.h

@@ -0,0 +1,40 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+/*
+ * Copyright (c) 2024, Arm Limited
+ */
+
+#ifndef PLATFORM_CONFIG_H
+#define PLATFORM_CONFIG_H
+
+#include <mm/generic_ram_layout.h>
+
+/* Make stacks aligned to data cache line length */
+#define STACK_ALIGNMENT			64
+
+#define DRAM0_BASE			UL(0x80000000)
+#define DRAM0_SIZE			UL(0x80000000)
+
+#define DRAM1_BASE			ULL(0x8080000000)
+#define DRAM1_SIZE			ULL(0x80000000)
+
+#define SYS_COUNTER_FREQ_IN_TICKS	UL(7372800)
+
+#define UART0_BASE			UL(0x2A400000)
+#define UART1_BASE			UL(0x2A410000)
+#define CONSOLE_UART_BASE		UART1_BASE
+#define UART_BAUDRATE			115200
+#define CONSOLE_BAUDRATE		UART_BAUDRATE
+#define CONSOLE_UART_CLK_IN_HZ		UL(7372800)
+
+/* GIC related constants */
+#define GICD_BASE			UL(0x30000000)
+#define GICC_BASE			UL(0x2C000000)
+
+ /* RD-1 AE topology related constants */
+#define RD1AE_MAX_CPUS_PER_CLUSTER	U(1)
+#define PLAT_ARM_CLUSTER_COUNT		U(1)
+#define PLAT_RD1AE_CHIP_COUNT		U(1)
+#define RD1AE_MAX_CLUSTERS_PER_CHIP	U(16)
+#define RD1AE_MAX_PE_PER_CPU		U(1)
+
+#endif /*PLATFORM_CONFIG_H*/

core/arch/arm/plat-rd1ae/rd1ae_core_pos.S

@@ -0,0 +1,32 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+/*
+ * Copyright (c) 2024, Arm Limited
+ */
+
+#include <asm.S>
+#include <arm.h>
+#include "platform_config.h"
+
+FUNC get_core_pos_mpidr , :
+        mov     x4, x0
+
+        /*
+         * The MT bit in MPIDR is always set for n1sdp and the
+         * affinity level 0 corresponds to thread affinity level.
+         */
+
+        /* Extract individual affinity fields from MPIDR */
+        ubfx    x0, x4, #MPIDR_AFF0_SHIFT, #MPIDR_AFFINITY_BITS
+        ubfx    x1, x4, #MPIDR_AFF1_SHIFT, #MPIDR_AFFINITY_BITS
+        ubfx    x2, x4, #MPIDR_AFF2_SHIFT, #MPIDR_AFFINITY_BITS
+        ubfx    x3, x4, #MPIDR_AFF3_SHIFT, #MPIDR_AFFINITY_BITS
+
+        /* Compute linear position */
+        mov     x4, #RD1AE_MAX_CLUSTERS_PER_CHIP
+        madd    x2, x3, x4, x2
+        mov     x4, #RD1AE_MAX_CPUS_PER_CLUSTER
+        madd    x1, x2, x4, x1
+        mov     x4, #RD1AE_MAX_PE_PER_CPU
+        madd    x0, x1, x4, x0
+        ret
+END_FUNC get_core_pos_mpidr

core/arch/arm/plat-rd1ae/sub.mk

@@ -0,0 +1,3 @@
+global-incdirs-y += .
+srcs-y += main.c
+srcs-y	+= rd1ae_core_pos.S

core/drivers/clk/clk-stm32-core.c

@@ -87,6 +87,14 @@ static void stm32_gate_endisable(uint16_t gate_id, bool enable)
 	}
 }
 
+void stm32_gate_set_init_state(uint16_t gate_id, bool enable)
+{
+	struct clk_stm32_priv __maybe_unused *priv = clk_stm32_get_priv();
+
+	assert(!priv->gate_cpt[gate_id]);
+	stm32_gate_endisable(gate_id, enable);
+}
+
 void stm32_gate_disable(uint16_t gate_id)
 {
 	struct clk_stm32_priv *priv = clk_stm32_get_priv();

core/drivers/clk/clk-stm32-core.h

@@ -120,6 +120,13 @@ TEE_Result stm32_gate_wait_ready(uint16_t gate_id, bool ready_on);
 TEE_Result stm32_gate_rdy_enable(uint16_t gate_id);
 TEE_Result stm32_gate_rdy_disable(uint16_t gate_id);
 
+/*
+ * Set gate to an enable or disable state without updating its
+ * refcount. This is exclusively intended to be used during initialization
+ * where refcount value are 0.
+ */
+void stm32_gate_set_init_state(uint16_t gate_id, bool enable);
+
 size_t stm32_mux_get_parent(uint32_t mux_id);
 TEE_Result stm32_mux_set_parent(uint16_t pid, uint8_t sel);
 

core/drivers/clk/clk-stm32mp13.c

@@ -964,10 +964,7 @@ static int stm32_clk_configure_clk(struct clk_stm32_priv *priv __maybe_unused,
 	if (stm32_mux_set_parent(mux, sel))
 		return -1;
 
-	if (enable)
-		stm32_gate_enable(gate);
-	else
-		stm32_gate_disable(gate);
+	stm32_gate_set_init_state(gate, enable);
 
 	return 0;
 }

core/drivers/gic.c

@@ -508,7 +508,7 @@ static void gic_init_base_addr(paddr_t gicc_base_pa, paddr_t gicd_base_pa,
 	vers &= GICD_PIDR2_ARCHREV_MASK;
 
 	if (IS_ENABLED(CFG_ARM_GICV3)) {
-		assert(vers == 3);
+		assert(vers == 4 || vers == 3);
 	} else {
 		assert(vers == 2 || vers == 1);
 		gicc_base = core_mmu_get_va(gicc_base_pa, MEM_AREA_IO_SEC,

core/drivers/stm32_rng.c

@@ -672,7 +672,7 @@ static TEE_Result stm32_rng_probe(const void *fdt, int offs,
 
 #if defined(CFG_STM32MP15)
 	/* Only STM32MP15 requires a software registering of RNG secure state */
-	if (etzpc_get_decprot(STM32MP1_ETZPC_RNG1_ID) == ETZPC_DECPROT_NS_RW)
+	if (IS_ENABLED(CFG_WITH_SOFTWARE_PRNG))
 		stm32mp_register_non_secure_periph_iomem(stm32_rng->base.pa);
 	else
 		stm32mp_register_secure_periph_iomem(stm32_rng->base.pa);

ldelf/ta_elf_rel.c

@@ -198,6 +198,9 @@ static TEE_Result resolve_sym_helper(const char *name, vaddr_t *val,
 		uint32_t *bucket = &hashtab[2];
 		uint32_t *chain = &bucket[nbuckets];
 
+		if (!nbuckets)
+			return TEE_ERROR_ITEM_NOT_FOUND;
+
 		hash = elf_hash(name);
 
 		for (n = bucket[hash % nbuckets]; n; n = chain[n]) {

mk/config.mk

@@ -127,7 +127,7 @@ CFG_OS_REV_REPORTS_GIT_SHA1 ?= y
 # with limited depth not including any tag, so there is really no guarantee
 # that TEE_IMPL_VERSION contains the major and minor revision numbers.
 CFG_OPTEE_REVISION_MAJOR ?= 4
-CFG_OPTEE_REVISION_MINOR ?= 3
+CFG_OPTEE_REVISION_MINOR ?= 4
 CFG_OPTEE_REVISION_EXTRA ?=
 
 # Trusted OS implementation version