update

debugger/chasing-bugs.md

@@ -1,7 +1,7 @@
 ---
 layout: default
 title: Chasing Bugs
-parent: Debugger
+parent: Debugger (kHyperDbg)
 nav_order: 3
 ---
 

debugger/debugger.md

@@ -1,6 +1,6 @@
 ---
 layout: default
-title: Debugger
+title: Debugger (kHyperDbg)
 nav_order: 3
 has_children: true
 permalink: /debugger

debugger/kernel-debugger-design.md

@@ -1,7 +1,7 @@
 ---
 layout: default
 title: Kernel Debugger Design
-parent: Debugger
+parent: Debugger (kHyperDbg)
 nav_order: 1
 ---
 

dslang/dslang.md

@@ -0,0 +1,61 @@
+---
+layout: default
+title: Debugger Script (dslang)
+nav_order: 4
+has_children: true
+permalink: /dslang
+---
+
+# Debugger Script (DS)
+
+Debugger Script
+{: .fs-6 .fw-300 }
+
+## Overview
+Debugger Script Language (dslang) is a powerful scripting language used within the HyperDbg debugger to automate debugging tasks, perform evaluations, and manipulate variables. This guide provides a detailed overview of the dsLang syntax, structure, and capabilities.
+
+## Scripting Language Components
+
+### Assumptions & Evaluations
+dslang scripts operate under specific assumptions:
+- Evaluation of expressions follows typical precedence rules.
+- Supports basic arithmetic, logical operations, and bitwise operations.
+
+### Variables & Assignments
+Variables in dslang can be declared and assigned values easily:
+- **Declaration**: Variables are implicitly declared upon first assignment.
+- **Types**: The language is type-aware, allowing for different data types including integers, strings, and more.
+- **Assignment**: Use the `=` operator for assignment.
+
+### Casting & Type-awareness
+dslang supports explicit type casting to ensure proper operations on different data types:
+- Cast operations can be performed using specific functions.
+
+### Conditionals & Loops
+Control flow in dslang is managed using standard conditional statements and loops:
+- **Conditionals**: `if`, `else if`, and `else` statements.
+- **Loops**: `while` and `for` loops for iteration.
+
+### Functions in dslang
+dslang provides a set of built-in functions categorized under various modules:
+- **Debugger Functions**: Control debugger operations like pausing.
+- **Events Functions**: Manage event handling and manipulation.
+- **Export Functions**: Functions like `print` and `printf` for output.
+- **Interlocked Functions**: Atomic operations for concurrency control.
+- **Memory Functions**: Manipulate and check memory addresses.
+- **Disassembler Functions**: Disassemble instructions.
+- **Spinlock Functions**: Manage spinlocks for synchronization.
+- **String Functions**: Handle string operations.
+
+## Examples
+dslang scripts can be used to perform various debugging tasks:
+- **View system state**: Access and display registers, memory, and variables.
+- **Change system state**: Modify registers, memory, and variables.
+- **Trace function calls**: Monitor and trace function calls.
+- **Conditional breakpoints**: Set breakpoints based on specific conditions.
+- **Patch execution flow**: Alter the normal sequence of execution.
+- **Access shared variables**: Manage variables across different cores.
+- **Count events**: Track the number of specific events.
+
+For more detailed examples and comprehensive documentation, visit the [HyperDbg Documentation](https://docs.hyperdbg.org/commands/scripting-language).
+

hwdbg/hwdbg.md

@@ -11,3 +11,14 @@ permalink: /hwdbg
 HyperDbg's Chip Debugger
 {: .fs-6 .fw-300 }
 
+## What is hwdbg?
+
+The **hwdbg** debugger chip generator is a gate-level debugging tool designed to make configurable and synthesizable hardware debuggers for white-box and black-box chip fuzzing, testing, and reverse engineering. The primary goal of **hwdbg** is to provide control over hardware, enabling monitoring and modification of signals down to the granular level of a single clock cycle. It is written in Chisel and Verilog.
+
+**hwdbg** is a highly customizable debugger designed to ease hardware debugging by bringing software debugging concepts into the hardware debugging domain. **hwdbg** aims to help with the complexities associated with debugging hardware, including chips and IP cores. Key features of **hwdbg** include the ability to step through the hardware design at the clock-cycle level, visualize waveforms, inspect values (e.g., like a logical analyzer), and modify signals. Moreover, it is synthesizable into [FPGAs](https://github.com/HyperDbg/hwdbg-fpga) and has the potential for fabrication into physical chips.
+
+## Source code
+
+The source code of hwdbg is available at:
+
+([https://github.com/HyperDbg/HyperDbg/tree/master/hwdbg](https://github.com/HyperDbg/HyperDbg/tree/master/hwdbg))