add sample top module

HyperDbg · Feb 23, 2024 · 6f5a6c9 · 6f5a6c9
1 parent f05e45d
commit 6f5a6c9
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diff --git a/src/main/scala/gcd/DecoupledGCD.scala b/src/main/scala/gcd/DecoupledGCD.scala
diff --git a/src/main/scala/gcd/GCD.scala b/src/main/scala/gcd/GCD.scala
diff --git a/src/main/scala/top.scala b/src/main/scala/top.scala
@@ -0,0 +1,28 @@
+package hwdbg
+
+import chisel3._
+import chisel3.util.Counter
+import circt.stage.ChiselStage
+
+class Blinky(freq: Int, startOn: Boolean = false) extends Module {
+  val io = IO(new Bundle {
+    val led0 = Output(Bool())
+  })
+  // Blink LED every second using Chisel built-in util.Counter
+  val led = RegInit(startOn.B)
+  val (_, counterWrap) = Counter(true.B, freq / 2)
+  when(counterWrap) {
+    led := ~led
+  }
+  io.led0 := led
+}
+
+object Main extends App {
+  // These lines generate the Verilog output
+  println(
+    ChiselStage.emitSystemVerilog(
+      new Blinky(1000),
+      firtoolOpts = Array("-disable-all-randomization", "-strip-debug-info")
+    )
+  )
+}