adjust sender packet header

HyperDbg · Apr 17, 2024 · 65a1b48 · 65a1b48
1 parent df2d3ed
commit 65a1b48
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Showing 7 changed files with 109 additions and 17 deletions.
diff --git a/src/main/scala/hwdbg/communication/interpreter.scala b/src/main/scala/hwdbg/communication/interpreter.scala
@@ -132,7 +132,7 @@ class DebuggerPacketInterpreter(
         //
         // Adjust address to read Checksum from BRAM (Not Used)
         //
-        regRdWrAddr := receivedPacketBuffer.Offset.checksum.U
+        regRdWrAddr := (MemoryCommunicationConfigurations.BASE_ADDRESS_OF_PS_TO_PL_COMMUNICATION + receivedPacketBuffer.Offset.checksum).U
 
         //
         // Goes to the next section
@@ -144,7 +144,7 @@ class DebuggerPacketInterpreter(
         //
         // Adjust address to read Indicator from BRAM
         //
-        regRdWrAddr := receivedPacketBuffer.Offset.indicator.U
+        regRdWrAddr := (MemoryCommunicationConfigurations.BASE_ADDRESS_OF_PS_TO_PL_COMMUNICATION + receivedPacketBuffer.Offset.indicator).U
 
         //
         // Goes to the next section
@@ -156,7 +156,7 @@ class DebuggerPacketInterpreter(
         //
         // Adjust address to read TypeOfThePacket from BRAM
         //
-        regRdWrAddr := receivedPacketBuffer.Offset.typeOfThePacket.U
+        regRdWrAddr := (MemoryCommunicationConfigurations.BASE_ADDRESS_OF_PS_TO_PL_COMMUNICATION + receivedPacketBuffer.Offset.typeOfThePacket).U
 
         //
         // Check whether the indicator is valid or not
@@ -185,12 +185,13 @@ class DebuggerPacketInterpreter(
         //
         // Adjust address to read RequestedActionOfThePacket from BRAM
         //
-        regRdWrAddr := receivedPacketBuffer.Offset.requestedActionOfThePacket.U
+        regRdWrAddr := (MemoryCommunicationConfigurations.BASE_ADDRESS_OF_PS_TO_PL_COMMUNICATION + receivedPacketBuffer.Offset.requestedActionOfThePacket).U
 
         //
         // Check whether the type of the packet is valid or not
         //
-        when(io.rdData === HyperDbgSharedConstants.INDICATOR_OF_HYPERDBG_PACKET.U) {
+        val packetType: DebuggerRemotePacketType.Value = DebuggerRemotePacketType.DEBUGGER_TO_DEBUGGEE_HARDWARE_LEVEL
+        when(io.rdData === packetType.id.U) {
 
           //
           // Type of packet is valid

diff --git a/src/main/scala/hwdbg/communication/sender.scala b/src/main/scala/hwdbg/communication/sender.scala
@@ -25,7 +25,7 @@ import hwdbg.constants._
 
 object DebuggerPacketSenderEnums {
   object State extends ChiselEnum {
-    val sIdle, sInit, sDone = Value
+    val sIdle, sWriteChecksum, sWriteIndicator, sWriteTypeOfThePacket, sWriteRequestedActionOfThePacket, sWriteSendingDataArray, sDone = Value
   }
 }
 
@@ -110,7 +110,7 @@ class DebuggerPacketSender(
         // Check whether the interrupt from the PS is received or not
         //
         when(risingEdgeBeginSendingBuffer === true.B) {
-          state := sInit
+          state := sWriteChecksum
         }
 
         //
@@ -123,14 +123,95 @@ class DebuggerPacketSender(
         regSendingSignalDone := false.B
 
       }
-      is(sInit) {}
+      is(sWriteChecksum) {
+
+        //
+        // Enable writing to the BRAM
+        //
+        regWrEna := true.B
+
+        //
+        // Adjust address to write Checksum to BRAM (Not Used)
+        //
+        regRdWrAddr := (MemoryCommunicationConfigurations.BASE_ADDRESS_OF_PL_TO_PS_COMMUNICATION + sendingPacketBuffer.Offset.checksum).U
+
+        //
+        // Adjust data to write Checksum
+        //
+        regWrData := 0.U // Checksum is ignored
+
+        //
+        // Goes to the next section
+        //
+        state := sWriteIndicator
+      }
+      is(sWriteIndicator) {
+
+        //
+        // Adjust address to write Indicator to BRAM
+        //
+        regRdWrAddr := (MemoryCommunicationConfigurations.BASE_ADDRESS_OF_PL_TO_PS_COMMUNICATION + sendingPacketBuffer.Offset.indicator).U
+
+        //
+        // Adjust data to write Indicator
+        //
+        regWrData := HyperDbgSharedConstants.INDICATOR_OF_HYPERDBG_PACKET.U
+
+        //
+        // Goes to the next section
+        //
+        state := sWriteTypeOfThePacket
+
+      }
+      is(sWriteTypeOfThePacket) {
+
+        //
+        // Adjust address to write type of packet to BRAM
+        //
+        regRdWrAddr := (MemoryCommunicationConfigurations.BASE_ADDRESS_OF_PL_TO_PS_COMMUNICATION + sendingPacketBuffer.Offset.typeOfThePacket).U
+
+        //
+        // Adjust data to write type of packet
+        //
+        val packetType: DebuggerRemotePacketType.Value = DebuggerRemotePacketType.DEBUGGEE_TO_DEBUGGER_HARDWARE_LEVEL
+        regWrData := packetType.id.U
+
+        //
+        // Goes to the next section
+        //
+        state := sWriteRequestedActionOfThePacket
+
+      }
+      is(sWriteRequestedActionOfThePacket) {
+
+        //
+        // Adjust address to write requested action of packet to BRAM
+        //
+        regRdWrAddr := (MemoryCommunicationConfigurations.BASE_ADDRESS_OF_PL_TO_PS_COMMUNICATION + sendingPacketBuffer.Offset.requestedActionOfThePacket).U
+
+        //
+        // Adjust data to write requested action of packet
+        //
+        regWrData := io.requestedActionOfThePacket
+
+        //
+        // Goes to the next section
+        //
+        state := sDone // sWriteSendingDataArray
+
+      }
       is(sDone) {
 
         //
         // Adjust the output bits
         //
         regSendingSignalDone := true.B
 
+        //
+        // Interrupt the PS
+        //
+        regPsOutInterrupt := true.B
+
         //
         // Go to the idle state
         //

diff --git a/src/main/scala/hwdbg/configs/configs.scala b/src/main/scala/hwdbg/configs/configs.scala
@@ -86,12 +86,22 @@ object DebuggerConfigurations {
 
 /**
  * @brief
- *   The constants for configuration
+ *   The constants for memory communication
  */
-object GeneralConfigurations {
+object MemoryCommunicationConfigurations {
 
   //
   // Default number of bytes used in initialized SRAM memory
   //
   val DEFAULT_CONFIGURATION_INITIALIZED_MEMORY_SIZE: Int = 8192 // 8 KB
+
+  //
+  // Base address of PS to PL SRAM communication memory
+  //
+  val BASE_ADDRESS_OF_PS_TO_PL_COMMUNICATION: Int = 0
+
+  //
+  // Base address of PL to PS SRAM communication memory
+  //
+  val BASE_ADDRESS_OF_PL_TO_PS_COMMUNICATION: Int = DEFAULT_CONFIGURATION_INITIALIZED_MEMORY_SIZE / 2
 }
diff --git a/src/main/scala/hwdbg/configs/constants.scala b/src/main/scala/hwdbg/configs/constants.scala
@@ -35,11 +35,11 @@ object HyperDbgSharedConstants {
 
 /**
  * @brief
- *   Enumeration for different packet types in HyperDbg packets
+ *   Enumeration for different packet types in HyperDbg packets (DEBUGGER_REMOTE_PACKET_TYPE)
  * @warning
  *   Used in HyperDbg
  */
-object DEBUGGER_REMOTE_PACKET_TYPE extends Enumeration {
+object DebuggerRemotePacketType extends Enumeration {
 
   //
   // Debugger to debuggee (vmx-root)

diff --git a/src/main/scala/hwdbg/libs/mem/init_mem.scala b/src/main/scala/hwdbg/libs/mem/init_mem.scala
@@ -25,7 +25,7 @@ class InitMemInline(
     memoryFile: String = TestingConfigurations.BRAM_INITIALIZATION_FILE_PATH,
     addrWidth: Int = DebuggerConfigurations.BLOCK_RAM_ADDR_WIDTH,
     width: Int = DebuggerConfigurations.BLOCK_RAM_DATA_WIDTH,
-    size: Int = GeneralConfigurations.DEFAULT_CONFIGURATION_INITIALIZED_MEMORY_SIZE
+    size: Int = MemoryCommunicationConfigurations.DEFAULT_CONFIGURATION_INITIALIZED_MEMORY_SIZE
 ) extends Module {
 
   val io = IO(new Bundle {
@@ -64,7 +64,7 @@ object InitMemInline {
       memoryFile: String = TestingConfigurations.BRAM_INITIALIZATION_FILE_PATH,
       addrWidth: Int = DebuggerConfigurations.BLOCK_RAM_ADDR_WIDTH,
       width: Int = DebuggerConfigurations.BLOCK_RAM_DATA_WIDTH,
-      size: Int = GeneralConfigurations.DEFAULT_CONFIGURATION_INITIALIZED_MEMORY_SIZE
+      size: Int = MemoryCommunicationConfigurations.DEFAULT_CONFIGURATION_INITIALIZED_MEMORY_SIZE
   )(
       enable: Bool,
       write: Bool,

diff --git a/src/main/scala/hwdbg/libs/mem/init_reg_mem_from_file.scala b/src/main/scala/hwdbg/libs/mem/init_reg_mem_from_file.scala
@@ -55,7 +55,7 @@ class InitRegMemFromFile(
     memoryFile: String = TestingConfigurations.BRAM_INITIALIZATION_FILE_PATH,
     addrWidth: Int = DebuggerConfigurations.BLOCK_RAM_ADDR_WIDTH,
     width: Int = DebuggerConfigurations.BLOCK_RAM_DATA_WIDTH,
-    size: Int = GeneralConfigurations.DEFAULT_CONFIGURATION_INITIALIZED_MEMORY_SIZE
+    size: Int = MemoryCommunicationConfigurations.DEFAULT_CONFIGURATION_INITIALIZED_MEMORY_SIZE
 ) extends Module {
 
   val io = IO(new Bundle {
@@ -93,7 +93,7 @@ object InitRegMemFromFile {
       memoryFile: String = TestingConfigurations.BRAM_INITIALIZATION_FILE_PATH,
       addrWidth: Int = DebuggerConfigurations.BLOCK_RAM_ADDR_WIDTH,
       width: Int = DebuggerConfigurations.BLOCK_RAM_DATA_WIDTH,
-      size: Int = GeneralConfigurations.DEFAULT_CONFIGURATION_INITIALIZED_MEMORY_SIZE
+      size: Int = MemoryCommunicationConfigurations.DEFAULT_CONFIGURATION_INITIALIZED_MEMORY_SIZE
   )(
       enable: Bool,
       write: Bool,

diff --git a/src/main/scala/top_test.scala b/src/main/scala/top_test.scala
@@ -72,7 +72,7 @@ class DebuggerModuleTestingBRAM(
       TestingConfigurations.BRAM_INITIALIZATION_FILE_PATH,
       bramAddrWidth,
       bramDataWidth,
-      GeneralConfigurations.DEFAULT_CONFIGURATION_INITIALIZED_MEMORY_SIZE
+      MemoryCommunicationConfigurations.DEFAULT_CONFIGURATION_INITIALIZED_MEMORY_SIZE
     )(
       bramEn,
       bramWrite,