add BRAM testing module

src/main/scala/hwdbg/configs/configs.scala

@@ -18,7 +18,7 @@ import chisel3._
 import chisel3.util._
 
 /** @brief
-  *   The constants for min-max tree
+  *   Design constants
   */
 object DebuggerConfigurations {
 
@@ -50,7 +50,7 @@ object DebuggerConfigurations {
 }
 
 /** @brief
-  *   The constants for min-max tree
+  *   The constants for configuration
   */
 object GeneralConfigurations {
 
@@ -59,3 +59,11 @@ object GeneralConfigurations {
   //
   val DEFAULT_CONFIGURATION_INITIALIZED_MEMORY_SIZE: Int = 8192 // 8 KB
 }
+
+/** @brief
+  *   The configuration constants for testing
+  */
+object TestingConfigurations {
+
+  val BRAM_INITIALIZATION_FILE_PATH: String = "/test.hex.txt"
+}

src/main/scala/hwdbg/libs/mem/init_mem.scala

@@ -31,7 +31,7 @@ class InitMemInline(
   val io = IO(new Bundle {
     val enable = Input(Bool())
     val write = Input(Bool())
-    val addr = Input(UInt(10.W))
+    val addr = Input(UInt(addrWidth.W))
     val dataIn = Input(UInt(width.W))
     val dataOut = Output(UInt(width.W))
   })
@@ -53,3 +53,51 @@ class InitMemInline(
       .otherwise { io.dataOut := rdwrPort }
   }
 }
+
+object InitMemInline {
+
+  def apply(
+      debug: Boolean = DebuggerConfigurations.ENABLE_DEBUG,
+      memoryFile: String = "",
+      addrWidth: Int = DebuggerConfigurations.BLOCK_RAM_ADDR_WIDTH,
+      width: Int = DebuggerConfigurations.BLOCK_RAM_DATA_WIDTH,
+      size: Int =
+        GeneralConfigurations.DEFAULT_CONFIGURATION_INITIALIZED_MEMORY_SIZE
+  )(
+      enable: Bool,
+      write: Bool,
+      addr: UInt,
+      dataIn: UInt
+  ): UInt = {
+
+    val initMemInlineModule = Module(
+      new InitMemInline(
+        debug,
+        memoryFile,
+        addrWidth,
+        width,
+        size
+      )
+    )
+
+    val dataOut = Wire(UInt(width.W))
+
+    //
+    // Configure the input signals
+    //
+    initMemInlineModule.io.enable := enable
+    initMemInlineModule.io.write := write
+    initMemInlineModule.io.addr := addr
+    initMemInlineModule.io.dataIn := dataIn
+
+    //
+    // Configure the input signals
+    //
+    dataOut := initMemInlineModule.io.dataOut
+
+    //
+    // Return the output result
+    //
+    dataOut
+  }
+}

src/main/scala/hwdbg/main.scala

@@ -0,0 +1,118 @@
+/** @file
+  *   main.scala
+  * @author
+  *   Sina Karvandi ([email protected])
+  * @brief
+  *   hwdbg's main debugger module
+  * @details
+  * @version 0.1
+  * @date
+  *   2024-04-04
+  *
+  * @copyright
+  *   This project is released under the GNU Public License v3.
+  */
+package hwdbg
+
+import chisel3._
+import chisel3.util.Counter
+import circt.stage.ChiselStage
+
+import hwdbg.configs._
+
+class DebuggerMain(
+    debug: Boolean = DebuggerConfigurations.ENABLE_DEBUG,
+    numberOfInputPins: Int = DebuggerConfigurations.NUMBER_OF_INPUT_PINS,
+    numberOfOutputPins: Int = DebuggerConfigurations.NUMBER_OF_OUTPUT_PINS,
+    bramAddrWidth: Int = DebuggerConfigurations.BLOCK_RAM_ADDR_WIDTH,
+    bramDataWidth: Int = DebuggerConfigurations.BLOCK_RAM_DATA_WIDTH
+) extends Module {
+  val io = IO(new Bundle {
+
+    //
+    // Chip signals
+    //
+    val en = Input(Bool()) // chip enable signal
+
+    //
+    // Input/Output signals
+    //
+    val inputPin = Input(Vec(numberOfInputPins, UInt((1.W)))) // input pins
+    val outputPin = Output(Vec(numberOfOutputPins, UInt((1.W)))) // output pins
+
+    //
+    // Interrupt signals (lines)
+    //
+    val plInSignal = Input(Bool()) // PS to PL signal
+    val psOutInterrupt = Output(Bool()) // PL to PS interrupt
+
+    //
+    // BRAM (Block RAM) ports
+    //
+    val rdAddr = Input(UInt(bramAddrWidth.W)) // read address
+    val rdData = Output(UInt(bramDataWidth.W)) // read data
+    val wrAddr = Input(UInt(bramAddrWidth.W)) // write address
+    val wrEna = Input(Bool()) // enable writing
+    val wrData = Input(UInt(bramDataWidth.W)) // write data
+
+  })
+
+  io.outputPin := io.inputPin
+
+}
+
+object DebuggerMain {
+
+  def apply(
+      debug: Boolean = DebuggerConfigurations.ENABLE_DEBUG,
+      numberOfInputPins: Int = DebuggerConfigurations.NUMBER_OF_INPUT_PINS,
+      numberOfOutputPins: Int = DebuggerConfigurations.NUMBER_OF_OUTPUT_PINS,
+      bramAddrWidth: Int = DebuggerConfigurations.BLOCK_RAM_ADDR_WIDTH,
+      bramDataWidth: Int = DebuggerConfigurations.BLOCK_RAM_DATA_WIDTH
+  )(
+      en: Bool,
+      inputPin: Vec[UInt],
+      psOutInterrupt: Bool,
+      rdAddr: UInt,
+      wrAddr: UInt,
+      wrEna: Bool,
+      wrData: UInt
+  ): (Vec[UInt], Bool, UInt) = {
+
+    val debuggerMainModule = Module(
+      new DebuggerMain(
+        debug,
+        numberOfInputPins,
+        numberOfOutputPins,
+        bramAddrWidth,
+        bramDataWidth
+      )
+    )
+
+    val outputPin = Wire(Vec(numberOfOutputPins, UInt((1.W))))
+    val psOutInterrupt = Wire(Bool())
+    val rdData = Wire(UInt(bramDataWidth.W))
+
+    //
+    // Configure the input signals
+    //
+    debuggerMainModule.io.en := en
+    debuggerMainModule.io.inputPin := inputPin
+    debuggerMainModule.io.rdAddr := rdAddr
+    debuggerMainModule.io.wrAddr := wrAddr
+    debuggerMainModule.io.wrEna := wrEna
+    debuggerMainModule.io.wrData := wrData
+
+    //
+    // Configure the input signals
+    //
+    outputPin := debuggerMainModule.io.outputPin
+    psOutInterrupt := debuggerMainModule.io.psOutInterrupt
+    rdData := debuggerMainModule.io.rdData
+
+    //
+    // Return the output result
+    //
+    (outputPin, psOutInterrupt, rdData)
+  }
+}

src/main/scala/top.scala

@@ -12,12 +12,11 @@
   * @copyright
   *   This project is released under the GNU Public License v3.
   */
-package hwdbg
-
 import chisel3._
 import chisel3.util.Counter
 import circt.stage.ChiselStage
 
+import hwdbg._
 import hwdbg.configs._
 
 class DebuggerModule(
@@ -32,39 +31,54 @@ class DebuggerModule(
     //
     // Chip signals
     //
-    /*
     val en = Input(Bool()) // chip enable signal
-     */
 
     //
     // Input/Output signals
     //
-
     val inputPin = Input(Vec(numberOfInputPins, UInt((1.W)))) // input pins
     val outputPin = Output(Vec(numberOfOutputPins, UInt((1.W)))) // output pins
 
     //
     // Interrupt signals (lines)
     //
-    /*
     val plInSignal = Input(Bool()) // PS to PL signal
     val psOutInterrupt = Output(Bool()) // PL to PS interrupt
-     */
 
     //
     // BRAM (Block RAM) ports
     //
-    /*
     val rdAddr = Input(UInt(bramAddrWidth.W)) // read address
     val rdData = Output(UInt(bramDataWidth.W)) // read data
     val wrAddr = Input(UInt(bramAddrWidth.W)) // write address
     val wrEna = Input(Bool()) // enable writing
     val wrData = Input(UInt(bramDataWidth.W)) // write data
-     */
 
   })
 
-  io.outputPin := io.inputPin
+  //
+  // Instantiate the debugger's main module
+  //
+  val (outputPin, psOutInterrupt, rdData) =
+    DebuggerMain(
+      debug,
+      numberOfInputPins,
+      numberOfOutputPins,
+      bramAddrWidth,
+      bramDataWidth
+    )(
+      io.en,
+      io.inputPin,
+      io.plInSignal,
+      io.rdAddr,
+      io.wrAddr,
+      io.wrEna,
+      io.wrData
+    )
+
+  io.outputPin := outputPin
+  io.psOutInterrupt := psOutInterrupt
+  io.rdData := rdData
 
 }
 

src/main/scala/top_test.scala

@@ -0,0 +1,101 @@
+/** @file
+  *   top_test.scala
+  * @author
+  *   Sina Karvandi ([email protected])
+  * @brief
+  *   hwdbg's top module (with BRAM) for testing
+  * @details
+  * @version 0.1
+  * @date
+  *   2024-04-04
+  *
+  * @copyright
+  *   This project is released under the GNU Public License v3.
+  */
+import chisel3._
+import chisel3.util.Counter
+import circt.stage.ChiselStage
+
+import hwdbg._
+import hwdbg.configs._
+import hwdbg.libs.mem._
+
+class DebuggerModuleTestingBRAM(
+    debug: Boolean = DebuggerConfigurations.ENABLE_DEBUG,
+    numberOfInputPins: Int = DebuggerConfigurations.NUMBER_OF_INPUT_PINS,
+    numberOfOutputPins: Int = DebuggerConfigurations.NUMBER_OF_OUTPUT_PINS,
+    bramAddrWidth: Int = DebuggerConfigurations.BLOCK_RAM_ADDR_WIDTH,
+    bramDataWidth: Int = DebuggerConfigurations.BLOCK_RAM_DATA_WIDTH
+) extends Module {
+  val io = IO(new Bundle {
+
+    //
+    // Chip signals
+    //
+    val en = Input(Bool()) // chip enable signal
+
+    //
+    // Input/Output signals
+    //
+    val inputPin = Input(Vec(numberOfInputPins, UInt((1.W)))) // input pins
+    val outputPin = Output(Vec(numberOfOutputPins, UInt((1.W)))) // output pins
+
+    //
+    // Interrupt signals (lines)
+    //
+    val plInSignal = Input(Bool()) // PS to PL signal
+    val psOutInterrupt = Output(Bool()) // PL to PS interrupt
+
+    //
+    // *** BRAM (Block RAM) ports are initialized from an external file ***
+    //
+
+  })
+
+  val bramEn = WireInit(false.B)
+  val bramWrite = WireInit(false.B)
+  val bramAddr = WireInit(0.U(bramAddrWidth.W))
+  val bramDataIn = WireInit(0.U(bramDataWidth.W))
+
+  //
+  // Instantiate the BRAM memory initializer module
+  //
+  val dataOut =
+    InitMemInline(
+      debug,
+      TestingConfigurations.BRAM_INITIALIZATION_FILE_PATH,
+      bramAddrWidth,
+      bramDataWidth,
+      GeneralConfigurations.DEFAULT_CONFIGURATION_INITIALIZED_MEMORY_SIZE
+    )(
+      bramEn,
+      bramWrite,
+      bramAddr,
+      bramDataIn
+    )
+
+  //
+  // Instantiate the debugger's main module
+  //
+  val (outputPin, psOutInterrupt, rdData) =
+    DebuggerMain(
+      debug,
+      numberOfInputPins,
+      numberOfOutputPins,
+      bramAddrWidth,
+      bramDataWidth
+    )(
+      io.en,
+      io.inputPin,
+      io.plInSignal,
+      bramAddr,
+      bramAddr,
+      bramEn,
+      dataOut
+    )
+
+  io.outputPin := outputPin
+  io.psOutInterrupt := psOutInterrupt
+  bramDataIn := rdData
+
+}