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fix simultaneous test for send and receive in synchronizer
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SinaKarvandi committed Apr 23, 2024
1 parent 3a5dbff commit 0c4edb6
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Showing 2 changed files with 24 additions and 3 deletions.
Original file line number Diff line number Diff line change
Expand Up @@ -119,6 +119,13 @@ async def SendReceiveSynchronizer_test(dut):
await RisingEdge(dut.clock)
dut.io_plInSignal.value = 0

#
# Activate sending logic to test whether the chip fails synchronizing signals or not
#
dut.io_beginSendingBuffer.value = 1
await RisingEdge(dut.clock)
dut.io_beginSendingBuffer.value = 0

#
# Wait until the receive operation is done (finished)
#
Expand Down Expand Up @@ -233,17 +240,23 @@ async def SendReceiveSynchronizer_test(dut):
else:
dut.io_readNextData.value = 0


#
# Go to the next clock cycle
#
await RisingEdge(dut.clock)


if test_number % 3 != 0:
dut.io_noNewDataReceiver.value = 1
await RisingEdge(dut.clock)
dut.io_noNewDataReceiver.value = 0

#
# Run extra waiting clocks
#
for _ in range(10):
await RisingEdge(dut.clock)

###############################################################
# #
# Sending Logic #
Expand All @@ -253,9 +266,10 @@ async def SendReceiveSynchronizer_test(dut):
dut._log.info("Enable sending data on the chip (" + str(test_number) + ")")

#
# Still there is data to send
# There is data to send
#
dut.io_noNewDataSender.value = 0
dut.io_beginSendingBuffer.value = 0

#
# Tell the sender to start sending data (This mainly operates based on
Expand All @@ -265,6 +279,13 @@ async def SendReceiveSynchronizer_test(dut):
await RisingEdge(dut.clock)
dut.io_beginSendingBuffer.value = 0

#
# Activate receiving logic to test whether the chip fails synchronizing signals or not
#
dut.io_plInSignal.value = 1
await RisingEdge(dut.clock)
dut.io_plInSignal.value = 0

#
# No new data at this stage
#
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Original file line number Diff line number Diff line change
Expand Up @@ -188,7 +188,7 @@ class SendReceiveSynchronizer(
//
// Go to the sender state
//
state := sReceiver
state := sSender

}.otherwise {

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