-
Notifications
You must be signed in to change notification settings - Fork 4
3. Gigabit Ethernet Interface
The GbE interface is a simple way to access FPGA internal registers and memory buffers from a PC. The GbE interface is always active, but is not required for operation. This interface is intended for slow controls and debugging and provides fast access to various spy buffers and registers.
The default IP address and MAC address is defined in oei/ethernet_interface.vhd and the contents of the one-time programmable EFUSE_USER register in the FPGA. Details on the mapping is in the Hardware section below.
The GbE interface accesses the user firmware components through a synchronous address data bus (A32D64) and thus all user firmware is memory mapped into this address space.
This information is unique and specific to each build, therefore it belongs with the firmware sources. See Memory_Map.md for details.
The FPGA firmware features an SPI slave that is used to communicate with the microcontroller. This SPI interface between the FPGA and the microcontroller replaces the 100BASE-X Ethernet inteface on the microcontroller.
Two FIFOs are used to attach this slave SPI to the GbE interface. The two FIFOs called CMD and RES and are memory mapped to a single address.
Command strings are written into the CMD FIFO (2k x 8). The command string must be less than 512 bytes ASCII data and terminated with 0x0d (CR) or 0x0a (LF). When the CMD FIFO has some data the SPI slave raises the SPI_IRQ line. The microcontroller then fetches the command string via the SPI interface, does the command, and writes any response string back to the SPI slave, which then stores it into the RES FIFO which can be read by the user through the GbE interface. If the user attempts to read an empty RES FIFO then 0xFF will be returned.
Also note that the DAPHNE microcontroller can hard reset the FPGA by pulling the RESETn line LOW momentarily. (There is a command to do this!)
This interface is based on the "off the shelf Ethernet Interface" developed at Fermilab by Ryan Rivera and Lorenzo Uplegger.