Add files via upload

tcl/target/gd32e50x.cfg

@@ -6,7 +6,7 @@
 # https://www.gigadevice.com/microcontroller/gd32e503cet6/
 
 #
-# gd32e50x devices support SWD transports only.
+# gd32e50x devices support both JTAG and SWD transports.
 #
 source [find target/swj-dp.tcl]
 source [find mem_helper.tcl]
@@ -37,13 +37,22 @@ if { [info exists FLASH_SIZE] } {
 if { [info exists CPUTAPID] } {
    set _CPUTAPID $CPUTAPID
 } else {
-   # this is the SW-DP tap id not the jtag tap id
-   set _CPUTAPID 0x0be12477
+   if { [using_jtag] } {
+      # See GD32E50x User Manual section 12.2.3
+      set _CPUTAPID 0x790007A3
+   } {
+      # this is the SW-DP tap id not the jtag tap id
+      set _CPUTAPID 0x0be12477
+   }
 }
 
 swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
 dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
 
+if {[using_jtag]} {
+   jtag newtap $_CHIPNAME bs -irlen 5
+}
+
 set _TARGETNAME $_CHIPNAME.cpu
 target create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap
 
@@ -56,6 +65,10 @@ flash bank $_FLASHNAME stm32f1x 0x08000000 $_FLASH_SIZE 0 0 $_TARGETNAME
 # SWD speed (may be updated to higher value in board config file)
 adapter speed 1000
 
+if {[using_jtag]} {
+ jtag_ntrst_delay 100
+}
+
 reset_config srst_nogate
 
 if {![using_hla]} {
@@ -65,10 +78,6 @@ if {![using_hla]} {
 }
 
 $_TARGETNAME configure -event examine-end {
-	# Debug clock enable
-	# RCU_APB2EN |= DBGMCUEN
-	mmw 0x40021018 0x00400000 0
-
 	# Stop watchdog counters during halt
 	# DBG_CTL |= WWDGT_HOLD | FWDGT_HOLD | STB_HOLD | DSLP_HOLD | SLP_HOLD
 	mmw 0xE0044004 0x00000307 0