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  • KTH Royal Institute of Technology
  • Stockholm, Sweden
  • 11:25 (UTC +01:00)
  • LinkedIn in/KarbonChen

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CSY-tvgo/README.md

👋 Hi, welcome to visit my&our open-source repositories. My nickname is Karbon.
📚 I am currently a double-degree master student of EIT Digital Master School. I am studying Embedded Systems at Università di Bologna and Kungliga Tekniska Högskolan.
🉑 My interests include embedded systems, edge AI applications & accelerators, and engineering education.
👨‍💻 I am also a remote member of VeriMake.

🔀 Most Used Languages: Chinese, English, C/C++, Python, Verilog, SystemVerilog……

More about me:
(in English) GitHub | LinkedIn | Google Scholar
(in Chinese) bilibili | WeChat 公众号 | VeriMake Forum

Popular repositories Loading

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    Classification, Object Detection, Adversarial Attack of Chinese Traffic Signs // 中式交通标志图片的分类、目标检测、对抗性攻击

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  5. Learn-Verilog-with-YADAN-Board Learn-Verilog-with-YADAN-Board Public

    Some examples of using Verilog to implement some simple digital designs on YADAN Board. // 用 Verilog 在 YADAN 开发板上实现一些简单数字系统的案例。

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  6. YOLOv4-Feature-Maps-Visualization YOLOv4-Feature-Maps-Visualization Public

    Display some of the feature maps of YOLOv4 (for artwork) // 展示 YOLOv4 中间层的一些特征图(用于艺术作品)

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