drm/asahi: render: Fix meta1_blocks calculation for MSAA

Block count needs to be computed with an extra factor of the sample count. Signed-off-by: Asahi Lina <[email protected]>
AsahiLinux · Jun 15, 2023 · 89651c2 · 89651c2
1 parent 185978b
commit 89651c2
Show file tree

Hide file tree

Showing 2 changed files with 5 additions and 3 deletions.
diff --git a/drivers/gpu/drm/asahi/hw/t600x.rs b/drivers/gpu/drm/asahi/hw/t600x.rs
@@ -62,7 +62,7 @@ pub(crate) const HWCONFIG_T6002: super::HwConfig = HwConfig {
     preempt3_size: 0x20,
     clustering: Some(HwClusteringConfig {
         meta1_blocksize: 0x44,
-        meta2_size: 0x190 * 8, // CHECK
+        meta2_size: 0xc0 * 8,
         meta3_size: 0x280 * 8,
         meta4_size: 0x30 * 16,
         max_splits: 16,

diff --git a/drivers/gpu/drm/asahi/queue/render.rs b/drivers/gpu/drm/asahi/queue/render.rs
@@ -134,9 +134,11 @@ impl super::Queue::ver {
         let tpc_size = (num_clusters * (4 * tpc_mtile_stride * mtiles) * layers) as usize;
 
         // No idea where this comes from, but it fits what macOS does...
-        // TODO: layers?
+        // GUESS: Number of 32K heap blocks to fit a 5-byte region header/pointer per tile?
+        // That would make a ton of sense...
+        // TODO: Layers? Why the sample count factor here?
         let meta1_blocks = if num_clusters > 1 {
-            div_ceil(align(tiles_x, 2) * align(tiles_y, 4), 0x1980)
+            div_ceil(align(tiles_x, 2) * align(tiles_y, 4) * cmdbuf.samples, 0x1980)
         } else {
             0
         };