One makefile can run sub each checker makefile

ivl_uvm_tests/ivl_uvm_ovl_tests/Makefile

@@ -0,0 +1,17 @@
+SUBDIRS = $(shell ls -d */)
+all:
+	for dir in $(SUBDIRS) ; do \
+        	make --no-print-directory -C  $$dir ; \
+	done
+
+clean:
+	for dir in $(SUBDIRS) ; do \
+        	make --no-print-directory -C  $$dir clean;\
+	done
+
+help:
+	for dir in $(SUBDIRS) ; do \
+        	make --no-print-directory -C  $$dir help;\
+	done
+
+

ivl_uvm_tests/ivl_uvm_ovl_tests/README

@@ -0,0 +1,41 @@
+---------------->>>>>>>>>>>>>>>>      Makefile Run flow
+Main makefile as below path
+/ivl_uvm-main/ivl_uvm_tests/ivl_uvm_ovl_tests/Makefile
+
+Main makefile will invoke  each checker subdir makefile as below names
+ivl_uvm_ovl_even_parity/Makefile
+
+
+
+---------------->>>>>>>>>>>>>>>>      To Run all checker
+
+make all  [this will run each chekcer makefiles (with pass and fail cases) ]
+make clean[ clean all the dumps]
+make help [this will show which are the targets for indiviadual checker]
+
+---------------->>>>>>>>>>>>>>>>      To Run individual checker
+
+[1] ovl_even_parity_pass
+% cd ivl_uvm_ovl_even_parity/
+
+% ls
+Makefile  flist  ivl_uvm_ovl_even_parity_fail.sv  ivl_uvm_ovl_even_parity_pass.sv
+
+% make
+rm -fr a.out *.log *.vcd tee
+iverilog -g2012 -s test -I/C/ivl_uvm-main1_sep_dir/ivl_uvm-main/ivl_uvm_std_ovl/ -f flist ivl_uvm_ovl_even_parity_pass.sv>& pass_comp.log
+vvp a.out >& pass_run.log
+iverilog -g2012 -s test -I/C/ivl_uvm-main1_sep_dir/ivl_uvm-main/ivl_uvm_std_ovl/ -f flist ivl_uvm_ovl_even_parity_fail.sv >& fail_comp.log
+vvp a.out >& fail_run.log
+(Targets -  clean pass fail ovl_fifo_index_pass ovl_fifo_index_fail ovl_even_parity_pass ovl_even_parity_fail ovl_win_change_pass ovl_win_change_fail )
+
+
+---------------->>>>>>>>>>>>>>>>      To see the waveform in GTK wave
+
+pacman -S mingw-w64-x86_64-gtkwave   --> to install GTK wave
+
+then after running the test with make it will create a dump.vcd
+
+gtkwave -o -t des.stems dump.vcd des.sav
+
+

ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_alw/flist

@@ -1,2 +1,3 @@
 ${IVL_UVM_HOME}/ivl_uvm_std_ovl/ivl_uvm_ovl_inc.v 
 ../ivl_uvm_ovl_clk_gen.sv
+#../ivl_uvm_ovl_fifo_dut.sv

ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_even_parity/Makefile

@@ -0,0 +1,19 @@
+all: clean ovl_even_parity_pass ovl_even_parity_fail help
+
+
+ovl_even_parity_pass: 
+	iverilog -g2012 -s test -I${IVL_UVM_HOME}/ivl_uvm_std_ovl/ -f flist ivl_uvm_ovl_even_parity_pass.sv>& pass_comp.log
+	vvp a.out >& pass_run.log
+
+ovl_even_parity_fail: 
+	iverilog -g2012 -s test -I${IVL_UVM_HOME}/ivl_uvm_std_ovl/ -f flist ivl_uvm_ovl_even_parity_fail.sv >& fail_comp.log
+	vvp a.out >& fail_run.log
+
+clean:
+	rm -fr a.out *.log *.vcd tee
+
+help:	
+	@echo "(Targets -  clean pass fail ovl_fifo_index_pass ovl_fifo_index_fail ovl_even_parity_pass ovl_even_parity_fail ovl_win_change_pass ovl_win_change_fail )"
+
+
+

ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_even_parity/flist

@@ -0,0 +1,3 @@
+${IVL_UVM_HOME}/ivl_uvm_std_ovl/ivl_uvm_ovl_inc.v 
+../ivl_uvm_ovl_clk_gen.sv
+#../ivl_uvm_ovl_fifo_dut.sv

ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_even_parity/ivl_uvm_ovl_even_parity_fail.sv

@@ -0,0 +1,78 @@
+// This is linear queue / FIFO
+// The queue length 1
+
+`timescale 1ns/1ns
+
+// TB
+module test;
+
+  logic clk, reset, wn, rn;
+  reg DATAIN;  
+
+  //enabling the wave dump
+  initial begin 
+      $dumpfile("dump.vcd");
+      $dumpvars(0, test);
+
+  end
+
+  // Instantiate OVL example - ovl_even_parity
+  ovl_even_parity u_ovl_even_parity (
+	                     .clock     (clk),
+			     .reset     (reset), 
+			     .enable    (1'b1),
+			     .test_expr (DATAIN)
+
+                 );
+
+
+
+
+initial begin
+    reset = 0;   wn = 0; rn = 0;
+    wait_clks(5);
+
+    reset = 1;
+    wait_clks(5);
+
+
+    $display("Start testing");
+
+    DATAIN = 0;
+    wait_clks(1);
+    $display("done parity injecting 1");
+
+    DATAIN = 0;
+    wait_clks(1);
+    $display("done parity injecting 2");
+
+    DATAIN = 0;
+    wait_clks(1);
+    $display("done parity injecting 3");
+
+
+    $display("real parity injecting 1");
+    DATAIN = 1;
+    wait_clks(1);
+
+
+    $display("real parity injecting 2");
+    DATAIN = 2;
+    wait_clks(1);
+
+    $display("Real parity injecting 3");
+    DATAIN = 99;
+    wait_clks(1);
+
+
+   $finish;
+
+end
+
+   task wait_clks(input int num_clks = 1);
+      repeat (num_clks) @(posedge clk);
+   endtask : wait_clks
+
+  ivl_uvm_ovl_clk_gen #(.FREQ_IN_MHZ(100)) u_clk_100 (clk);
+
+endmodule

ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_even_parity/ivl_uvm_ovl_even_parity_pass.sv

@@ -0,0 +1,63 @@
+// This is linear queue / FIFO
+// The queue length 1
+
+`timescale 1ns/1ns
+
+// TB
+module test;
+
+  logic clk, reset, wn, rn;
+  reg DATAIN;  
+
+  //enabling the wave dump
+  initial begin 
+      $dumpfile("dump.vcd");
+      $dumpvars(0, test);
+
+  end
+
+  // Instantiate OVL example - ovl_even_parity
+  ovl_even_parity u_ovl_even_parity (
+	                     .clock     (clk),
+			     .reset     (reset), 
+			     .enable    (1'b1),
+			     .test_expr (DATAIN)
+
+                 );
+
+
+
+
+initial begin
+    reset = 0;   wn = 0; rn = 0;
+    wait_clks(5);
+
+
+
+    $display("Start testing");
+
+    DATAIN = 0;
+    wait_clks(1);
+    $display("done parity injecting 1");
+
+    DATAIN = 0;
+    wait_clks(1);
+    $display("done parity injecting 2");
+
+    DATAIN = 0;
+    wait_clks(1);
+    $display("done parity injecting 3");
+
+
+
+   $finish;
+
+end
+
+   task wait_clks(input int num_clks = 1);
+      repeat (num_clks) @(posedge clk);
+   endtask : wait_clks
+
+  ivl_uvm_ovl_clk_gen #(.FREQ_IN_MHZ(100)) u_clk_100 (clk);
+
+endmodule

ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_fifo_index/Makefile

@@ -0,0 +1,18 @@
+all: clean ovl_fifo_index_pass ovl_fifo_index_fail help
+
+ovl_fifo_index_pass: 
+	iverilog -g2012 -s test -I${IVL_UVM_HOME}/ivl_uvm_std_ovl/ -f flist ivl_uvm_ovl_fifo_index_pass.sv>& pass_comp.log
+	vvp a.out >& pass_run.log
+
+ovl_fifo_index_fail: 
+	iverilog -g2012 -s test -I${IVL_UVM_HOME}/ivl_uvm_std_ovl/ -f flist ivl_uvm_ovl_fifo_index_fail.sv >& fail_comp.log
+	vvp a.out >& fail_run.log
+
+clean:
+	rm -fr a.out *.log *.vcd tee
+
+help:	
+	@echo "(Targets -  clean pass fail ovl_fifo_index_pass ovl_fifo_index_fail ovl_even_parity_pass ovl_even_parity_fail ovl_win_change_pass ovl_win_change_fail )"
+
+
+

ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_fifo_index/flist

@@ -0,0 +1,3 @@
+${IVL_UVM_HOME}/ivl_uvm_std_ovl/ivl_uvm_ovl_inc.v 
+../ivl_uvm_ovl_clk_gen.sv
+#../ivl_uvm_ovl_fifo_dut.sv

ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_fifo_index/ivl_uvm_ovl_fifo_index_fail.sv

@@ -0,0 +1,96 @@
+// This is linear queue / FIFO
+// The queue length 1
+
+`timescale 1ns/1ns
+
+// TB
+module test;
+
+  logic clk, reset, wn, rn;
+  reg [7:0] DATAIN;  
+
+  //enabling the wave dump
+  initial begin 
+      $dumpfile("dump.vcd");
+      $dumpvars(0, test);
+
+  end
+
+     // Instantiate OVL example - ovl_fifo_index
+   ovl_fifo_index u_ovl_fifo_index ( 
+			     .clock     (clk),
+			     .reset     (reset), 
+			     .enable    (1'b1),
+			     .push      (wn),
+			     .pop       (rn)
+			     );
+
+  // Instantiate OVL example - ovl_even_parity
+//  ovl_even_parity u_ovl_even_parity (
+//                 .clock     (clk),
+//			     .reset     (reset), 
+//			     .enable    (1'b1),
+//			     .test_expr (DATAOUT[0])
+//      
+//                 );
+
+
+
+
+initial begin
+    reset = 0;   wn = 0; rn = 0;
+    wait_clks(5);
+
+    reset = 1;
+    wait_clks(5);
+
+
+    $display("Start testing");
+    $display("Underflow injecting");
+    wn = 0; rn = 1;
+    wait_clks(5);
+
+    wn = 1; rn = 0;
+    wait_clks(5);
+
+    $display("overflow injecting");
+    wn = 1; rn = 0;
+    wait_clks(5);
+
+    wn = 1; rn = 0;
+    wait_clks(5);
+
+    wn = 1; rn = 0;
+    wait_clks(5);
+
+
+    wn = 1; rn = 0;
+    wait_clks(5);
+
+
+    wn = 1; rn = 0;
+    wait_clks(5);
+
+
+    wn = 1; rn = 0;
+    wait_clks(5);
+
+
+    wn = 1; rn = 0;
+    wait_clks(5);
+
+
+    wn = 1; rn = 0;
+    wait_clks(5);
+
+   $finish;
+
+end
+
+   task wait_clks(input int num_clks = 1);
+      repeat (num_clks) @(posedge clk);
+   endtask : wait_clks
+
+  ivl_uvm_ovl_clk_gen #(.FREQ_IN_MHZ(100)) u_clk_100 (clk);
+
+endmodule