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Releases: ANL-CESAR/RSBench

RSBench v13

08 Dec 20:24
@jtramm jtramm
v13
23d3ff9
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Adds a HIP version along with other small changes.

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RSBench v12

01 Aug 16:16
@jtramm jtramm
v12
71b6fff
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RSBench v12

This update adds formal support for accelerator architectures using a variety of programming models. RSBench is now implemented using five different models, each in their own source base:

  • OpenMP threading
  • OpenMP target offloading
  • CUDA
  • OpenCL
  • SYCL

Full details on the changes introduced in v12 can be found in CHANGES.txt file.

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RSBench v11

19 Sep 14:12
@jtramm jtramm
v11
cf42d27
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RSBench v11

See CHANGES for details.

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RSBench v10

09 Aug 16:32
@jtramm jtramm
v10
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RSBench v10

See CHANGES file for details.

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RSBench v2

06 May 22:17
@jtramm jtramm
v2
9be716e
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RSBench v2 
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