diff --git a/boards/renesas/ek_ra8d1/ek_ra8d1.dts b/boards/renesas/ek_ra8d1/ek_ra8d1.dts index 1acd07432209..69a2101c54ba 100644 --- a/boards/renesas/ek_ra8d1/ek_ra8d1.dts +++ b/boards/renesas/ek_ra8d1/ek_ra8d1.dts @@ -56,20 +56,23 @@ }; &pll { - clocks = <&xtal>; - div = <2>; - mul = <96 0>; - divp = <2>; - freqp = ; - divq = <2>; - freqq = ; - divr = <2>; - freqr = ; status = "okay"; + pllp { + status = "okay"; + }; + + pllq { + status = "okay"; + }; + + pllr { + status = "okay"; + }; }; + &sciclk { - clocks = <&pll>; + clocks = <&pllp>; div = <4>; status = "okay"; }; diff --git a/boards/renesas/ek_ra8m1/ek_ra8m1.dts b/boards/renesas/ek_ra8m1/ek_ra8m1.dts index 3d0c8dba180e..3c0f654e4ece 100644 --- a/boards/renesas/ek_ra8m1/ek_ra8m1.dts +++ b/boards/renesas/ek_ra8m1/ek_ra8m1.dts @@ -79,20 +79,23 @@ }; &pll { - clocks = <&xtal>; - div = <2>; - mul = <96 0>; - divp = <2>; - freqp = ; - divq = <2>; - freqq = ; - divr = <2>; - freqr = ; status = "okay"; + pllp { + status = "okay"; + }; + + pllq { + status = "okay"; + }; + + pllr { + status = "okay"; + }; }; + &sciclk { - clocks = <&pll>; + clocks = <&pllp>; div = <4>; status = "okay"; }; diff --git a/boards/renesas/mck_ra8t1/mck_ra8t1.dts b/boards/renesas/mck_ra8t1/mck_ra8t1.dts index 440e4d78241f..dc1a621bc117 100644 --- a/boards/renesas/mck_ra8t1/mck_ra8t1.dts +++ b/boards/renesas/mck_ra8t1/mck_ra8t1.dts @@ -60,20 +60,22 @@ }; &pll { - clocks = <&xtal>; - div = <2>; - mul = <80 0>; - divp = <2>; - freqp = ; - divq = <2>; - freqq = ; - divr = <2>; - freqr = ; status = "okay"; + pllp { + status = "okay"; + }; + + pllq { + status = "okay"; + }; + + pllr { + status = "okay"; + }; }; &sciclk { - clocks = <&pll>; + clocks = <&pllp>; div = <4>; status = "okay"; }; diff --git a/drivers/clock_control/clock_control_renesas_ra_cgc.c b/drivers/clock_control/clock_control_renesas_ra_cgc.c index 79da94a6d278..4ed4bb30daaa 100644 --- a/drivers/clock_control/clock_control_renesas_ra_cgc.c +++ b/drivers/clock_control/clock_control_renesas_ra_cgc.c @@ -58,7 +58,7 @@ static int clock_control_renesas_ra_get_rate(const struct device *dev, clock_con } clk_src_rate = R_BSP_SourceClockHzGet(config->clk_src); - clk_div_val = R_FSP_ClockDividerGet(config->clk_div); + clk_div_val = config->clk_div; *rate = clk_src_rate / clk_div_val; return 0; } @@ -94,7 +94,7 @@ static const struct clock_control_driver_api clock_control_reneas_ra_api = { DT_NODE_HAS_PROP(node_id, clocks), \ (RA_CGC_CLK_SRC(DT_CLOCKS_CTLR(node_id))), \ (RA_CGC_CLK_SRC(DT_CLOCKS_CTLR(DT_PARENT(node_id))))), \ - .clk_div = RA_CGC_CLK_DIV(node_id, div, 1)}; \ + .clk_div = DT_PROP(node_id, div)}; \ DEVICE_DT_DEFINE(node_id, &clock_control_ra_init_pclk, NULL, NULL, \ &node_id##_cfg, PRE_KERNEL_1, \ CONFIG_KERNEL_INIT_PRIORITY_OBJECTS, \ diff --git a/dts/arm/renesas/ra/ra8/r7fa8d1xh.dtsi b/dts/arm/renesas/ra/ra8/r7fa8d1xh.dtsi index 3db4898ccb2f..cd2b62c0924a 100644 --- a/dts/arm/renesas/ra/ra8/r7fa8d1xh.dtsi +++ b/dts/arm/renesas/ra/ra8/r7fa8d1xh.dtsi @@ -52,12 +52,30 @@ clocks = <&xtal>; div = <2>; mul = <96 0>; - divp = <2>; - freqp = ; - divq = <2>; - freqq = ; - divr = <2>; - freqr = ; + + pllp: pllp { + compatible = "renesas,ra-cgc-pll-out"; + div = <2>; + freq = ; + status = "disabled"; + #clock-cells = <0>; + }; + + pllq: pllq { + compatible = "renesas,ra-cgc-pll-out"; + div = <2>; + freq = ; + status = "disabled"; + #clock-cells = <0>; + }; + + pllr: pllr { + compatible = "renesas,ra-cgc-pll-out"; + div = <2>; + freq = ; + status = "disabled"; + #clock-cells = <0>; + }; status = "disabled"; }; @@ -68,12 +86,30 @@ /* PLL2 */ div = <2>; mul = <96 0>; - divp = <2>; - freqp = ; - divq = <2>; - freqq = ; - divr = <2>; - freqr = ; + + pll2p: pll2p { + compatible = "renesas,ra-cgc-pll-out"; + div = <2>; + freq = ; + status = "disabled"; + #clock-cells = <0>; + }; + + pll2q: pll2q { + compatible = "renesas,ra-cgc-pll-out"; + div = <2>; + freq = ; + status = "disabled"; + #clock-cells = <0>; + }; + + pll2r: pll2r { + compatible = "renesas,ra-cgc-pll-out"; + div = <2>; + freq = ; + status = "disabled"; + #clock-cells = <0>; + }; status = "disabled"; }; @@ -84,7 +120,7 @@ reg-names = "MSTPA", "MSTPB","MSTPC", "MSTPD", "MSTPE"; #clock-cells = <0>; - clocks = <&pll>; + clocks = <&pllp>; status = "okay"; cpuclk: cpuclk { diff --git a/dts/arm/renesas/ra/ra8/r7fa8m1xh.dtsi b/dts/arm/renesas/ra/ra8/r7fa8m1xh.dtsi index cb22fd3357a5..aedecdd38ff9 100644 --- a/dts/arm/renesas/ra/ra8/r7fa8m1xh.dtsi +++ b/dts/arm/renesas/ra/ra8/r7fa8m1xh.dtsi @@ -52,12 +52,30 @@ clocks = <&xtal>; div = <2>; mul = <96 0>; - divp = <2>; - freqp = ; - divq = <2>; - freqq = ; - divr = <2>; - freqr = ; + + pllp: pllp { + compatible = "renesas,ra-cgc-pll-out"; + div = <2>; + freq = ; + status = "disabled"; + #clock-cells = <0>; + }; + + pllq: pllq { + compatible = "renesas,ra-cgc-pll-out"; + div = <2>; + freq = ; + status = "disabled"; + #clock-cells = <0>; + }; + + pllr: pllr { + compatible = "renesas,ra-cgc-pll-out"; + div = <2>; + freq = ; + status = "disabled"; + #clock-cells = <0>; + }; status = "disabled"; }; @@ -68,12 +86,30 @@ /* PLL2 */ div = <2>; mul = <96 0>; - divp = <2>; - freqp = ; - divq = <2>; - freqq = ; - divr = <2>; - freqr = ; + + pll2p: pll2p { + compatible = "renesas,ra-cgc-pll-out"; + div = <2>; + freq = ; + status = "disabled"; + #clock-cells = <0>; + }; + + pll2q: pll2q { + compatible = "renesas,ra-cgc-pll-out"; + div = <2>; + freq = ; + status = "disabled"; + #clock-cells = <0>; + }; + + pll2r: pll2r { + compatible = "renesas,ra-cgc-pll-out"; + div = <2>; + freq = ; + status = "disabled"; + #clock-cells = <0>; + }; status = "disabled"; }; @@ -84,7 +120,7 @@ reg-names = "MSTPA", "MSTPB","MSTPC", "MSTPD", "MSTPE"; #clock-cells = <0>; - clocks = <&pll>; + clocks = <&pllp>; status = "okay"; cpuclk: cpuclk { diff --git a/dts/arm/renesas/ra/ra8/r7fa8t1xh.dtsi b/dts/arm/renesas/ra/ra8/r7fa8t1xh.dtsi index de851f6bf47e..a2013deab259 100644 --- a/dts/arm/renesas/ra/ra8/r7fa8t1xh.dtsi +++ b/dts/arm/renesas/ra/ra8/r7fa8t1xh.dtsi @@ -47,17 +47,33 @@ pll: pll { compatible = "renesas,ra-cgc-pll"; #clock-cells = <0>; - - /* PLL */ clocks = <&xtal>; div = <2>; mul = <80 0>; - divp = <2>; - freqp = ; - divq = <2>; - freqq = ; - divr = <2>; - freqr = ; + + pllp: pllp { + compatible = "renesas,ra-cgc-pll-out"; + div = <2>; + freq = ; + status = "disabled"; + #clock-cells = <0>; + }; + + pllq: pllq { + compatible = "renesas,ra-cgc-pll-out"; + div = <2>; + freq = ; + status = "disabled"; + #clock-cells = <0>; + }; + + pllr: pllr { + compatible = "renesas,ra-cgc-pll-out"; + div = <2>; + freq = ; + status = "disabled"; + #clock-cells = <0>; + }; status = "disabled"; }; @@ -65,15 +81,32 @@ compatible = "renesas,ra-cgc-pll"; #clock-cells = <0>; - /* PLL2 */ div = <2>; mul = <96 0>; - divp = <2>; - freqp = ; - divq = <2>; - freqq = ; - divr = <2>; - freqr = ; + + pll2p: pll2p { + compatible = "renesas,ra-cgc-pll-out"; + div = <2>; + freq = ; + status = "disabled"; + #clock-cells = <0>; + }; + + pll2q: pll2q { + compatible = "renesas,ra-cgc-pll-out"; + div = <2>; + freq = ; + status = "disabled"; + #clock-cells = <0>; + }; + + pll2r: pll2r { + compatible = "renesas,ra-cgc-pll-out"; + div = <2>; + freq = ; + status = "disabled"; + #clock-cells = <0>; + }; status = "disabled"; }; @@ -84,7 +117,7 @@ reg-names = "MSTPA", "MSTPB","MSTPC", "MSTPD", "MSTPE"; #clock-cells = <0>; - clocks = <&pll>; + clocks = <&pllp>; status = "okay"; cpuclk: cpuclk { diff --git a/dts/bindings/clock/renesas,ra-cgc-pll-out.yaml b/dts/bindings/clock/renesas,ra-cgc-pll-out.yaml new file mode 100644 index 000000000000..2d35a714899b --- /dev/null +++ b/dts/bindings/clock/renesas,ra-cgc-pll-out.yaml @@ -0,0 +1,19 @@ +# Copyright (c) 2024 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +description: Renesas RA Clock Generation Circuit PLL Clock out line + +compatible: "renesas,ra-cgc-pll-out" + +include: [clock-controller.yaml, base.yaml] + +properties: + div: + required: true + type: int + freq: + required: true + type: int + + "#clock-cells": + const: 0 diff --git a/dts/bindings/clock/renesas,ra-cgc-pll.yaml b/dts/bindings/clock/renesas,ra-cgc-pll.yaml index 7c959b6a01db..38d1dc410a23 100644 --- a/dts/bindings/clock/renesas,ra-cgc-pll.yaml +++ b/dts/bindings/clock/renesas,ra-cgc-pll.yaml @@ -16,18 +16,6 @@ properties: mul: required: true type: array - divp: - type: int - freqp: - type: int - divq: - type: int - freqq: - type: int - divr: - type: int - freqr: - type: int "#clock-cells": const: 0 diff --git a/include/zephyr/drivers/clock_control/renesas_ra_cgc.h b/include/zephyr/drivers/clock_control/renesas_ra_cgc.h index a7f147382fdc..1c29c9c893e7 100644 --- a/include/zephyr/drivers/clock_control/renesas_ra_cgc.h +++ b/include/zephyr/drivers/clock_control/renesas_ra_cgc.h @@ -37,14 +37,27 @@ #define RA_CGC_DIV_PCLKD(n) UTIL_CAT(BSP_CLOCKS_SYS_CLOCK_DIV_, n) #define RA_CGC_DIV_PCLKE(n) UTIL_CAT(BSP_CLOCKS_SYS_CLOCK_DIV_, n) #define RA_CGC_DIV_PLL(n) UTIL_CAT(BSP_CLOCKS_PLL_DIV_, n) +#define RA_CGC_DIV_PLLP(n) UTIL_CAT(BSP_CLOCKS_PLL_DIV_, n) +#define RA_CGC_DIV_PLLQ(n) UTIL_CAT(BSP_CLOCKS_PLL_DIV_, n) +#define RA_CGC_DIV_PLLR(n) UTIL_CAT(BSP_CLOCKS_PLL_DIV_, n) #define RA_CGC_DIV_PLL2(n) UTIL_CAT(BSP_CLOCKS_PLL_DIV_, n) +#define RA_CGC_DIV_PLL2P(n) UTIL_CAT(BSP_CLOCKS_PLL_DIV_, n) +#define RA_CGC_DIV_PLL2Q(n) UTIL_CAT(BSP_CLOCKS_PLL_DIV_, n) +#define RA_CGC_DIV_PLL2R(n) UTIL_CAT(BSP_CLOCKS_PLL_DIV_, n) #define RA_CGC_DIV_SCICLK(n) UTIL_CAT(BSP_CLOCKS_SCI_CLOCK_DIV_, n) #define RA_CGC_DIV_SPICLK(n) UTIL_CAT(BSP_CLOCKS_SPI_CLOCK_DIV_, n) #define RA_CGC_DIV_U60CLK(n) UTIL_CAT(BSP_CLOCKS_USB60_CLOCK_DIV_, n) #define RA_CGC_DIV_UCLK(n) UTIL_CAT(BSP_CLOCKS_USB_CLOCK_DIV_, n) #define BSP_CLOCKS_SOURCE_PLL BSP_CLOCKS_SOURCE_CLOCK_PLL -#define BSP_CLOCKS_SOURCE_PLL2 BSP_CLOCKS_SOURCE_CLOCK_PLL +#define BSP_CLOCKS_SOURCE_PLLP BSP_CLOCKS_SOURCE_CLOCK_PLL +#define BSP_CLOCKS_SOURCE_PLLQ BSP_CLOCKS_SOURCE_CLOCK_PLL1Q +#define BSP_CLOCKS_SOURCE_PLLR BSP_CLOCKS_SOURCE_CLOCK_PLL1R + +#define BSP_CLOCKS_SOURCE_PLL2 BSP_CLOCKS_SOURCE_CLOCK_PLL2 +#define BSP_CLOCKS_SOURCE_PLL2P BSP_CLOCKS_SOURCE_CLOCK_PLL2 +#define BSP_CLOCKS_SOURCE_PLL2Q BSP_CLOCKS_SOURCE_CLOCK_PLL2Q +#define BSP_CLOCKS_SOURCE_PLL2R BSP_CLOCKS_SOURCE_CLOCK_PLL2R #define BSP_CLOCKS_CLKOUT_DIV_1 (0) #define BSP_CLOCKS_CLKOUT_DIV_2 (1) diff --git a/west.yml b/west.yml index 376b88186860..0f0489352653 100644 --- a/west.yml +++ b/west.yml @@ -214,7 +214,7 @@ manifest: - hal - name: hal_renesas path: modules/hal/renesas - revision: 3dafd030046f8d6f8a26080e9b9c1bcc92d45999 + revision: 10326518701e25bf336a2eaeb8b5820110e4e6a3 groups: - hal - name: hal_rpi_pico