diff --git a/boards/riscv/hpm6750evkmini/CMakeLists.txt b/boards/riscv/hpm6750evkmini/CMakeLists.txt new file mode 100644 index 000000000000..d3be95f6d30d --- /dev/null +++ b/boards/riscv/hpm6750evkmini/CMakeLists.txt @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: Apache-2.0 + +zephyr_sources_ifdef(CONFIG_XIP bootstartup.c) diff --git a/boards/riscv/hpm6750evkmini/Kconfig.board b/boards/riscv/hpm6750evkmini/Kconfig.board new file mode 100644 index 000000000000..3eac69ef7cd2 --- /dev/null +++ b/boards/riscv/hpm6750evkmini/Kconfig.board @@ -0,0 +1,8 @@ +# Copyright (c) 2022 HPMicro +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_HPM6750EVKMINI + bool "HPMicro HPM6750EVKMINI" + depends on SOC_SERIES_ANDES_HPMICRO + depends on SOC_HPM675X + select CPU_HAS_FPU_DOUBLE_PRECISION diff --git a/boards/riscv/hpm6750evkmini/Kconfig.defconfig b/boards/riscv/hpm6750evkmini/Kconfig.defconfig new file mode 100644 index 000000000000..d4fe9f5b4039 --- /dev/null +++ b/boards/riscv/hpm6750evkmini/Kconfig.defconfig @@ -0,0 +1,17 @@ +# Copyright (c) 2022 HPMicro +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_HPM6750EVKMINI + +DT_CHOSEN_Z_CODE_PARTITION := zephyr,code-partition + +config BOARD + default "hpm6750evkmini" + +config FLASH_LOAD_OFFSET + default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) + +config FLASH_LOAD_SIZE + default $(dt_chosen_reg_size_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) + +endif # BOARD_HPM6750EVKMINI diff --git a/boards/riscv/hpm6750evkmini/board.cmake b/boards/riscv/hpm6750evkmini/board.cmake new file mode 100644 index 000000000000..e295c8969163 --- /dev/null +++ b/boards/riscv/hpm6750evkmini/board.cmake @@ -0,0 +1,11 @@ +# SPDX-License-Identifier: Apache-2.0 + +if(NOT CONFIG_XIP) +board_runner_args(openocd "--use-elf") +endif() +board_runner_args(openocd "--config=${BOARD_DIR}/support/probes/ft2232.cfg" + "--config=${BOARD_DIR}/support/soc/hpm6750-single-core.cfg" + "--config=${BOARD_DIR}/support/boards/hpm6750evkmini.cfg") +board_runner_args(openocd --target-handle=_CHIPNAME.cpu0) + +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) diff --git a/boards/riscv/hpm6750evkmini/bootstartup.c b/boards/riscv/hpm6750evkmini/bootstartup.c new file mode 100644 index 000000000000..3a809c491303 --- /dev/null +++ b/boards/riscv/hpm6750evkmini/bootstartup.c @@ -0,0 +1,73 @@ +/* + * Copyright (c) 2022 HPMicro + * + * SPDX-License-Identifier: Apache-2.0 + * + */ + +#include + +#ifdef CONFIG_XIP +/** + * @brief FLASH configuration option definitions: + * option[0]: + * [31:16] 0xfcf9 - FLASH configuration option tag + * [15:4] 0 - Reserved + * [3:0] option words (exclude option[0]) + * option[1]: + * [31:28] Flash probe type + * 0 - SFDP SDR / 1 - SFDP DDR + * 2 - 1-4-4 Read (0xEB, 24-bit address) / 3 - 1-2-2 Read(0xBB, 24-bit address) + * 4 - HyperFLASH 1.8V / 5 - HyperFLASH 3V + * 6 - OctaBus DDR (SPI -> OPI DDR) + * 8 - Xccela DDR (SPI -> OPI DDR) + * 10 - EcoXiP DDR (SPI -> OPI DDR) + * [27:24] Command Pads after Power-on Reset + * 0 - SPI / 1 - DPI / 2 - QPI / 3 - OPI + * [23:20] Command Pads after Configuring FLASH + * 0 - SPI / 1 - DPI / 2 - QPI / 3 - OPI + * [19:16] Quad Enable Sequence (for the device support SFDP 1.0 only) + * 0 - Not needed + * 1 - QE bit is at bit 6 in Status Register 1 + * 2 - QE bit is at bit1 in Status Register 2 + * 3 - QE bit is at bit7 in Status Register 2 + * 4 - QE bit is at bit1 in Status Register 2 and should be programmed by 0x31 + * [15:8] Dummy cycles + * 0 - Auto-probed / detected / default value + * Others - User specified value, for DDR read, the dummy cycles should be + * 2 * cycles on FLASH datasheet + * [7:4] Misc. + * 0 - Not used + * 1 - SPI mode + * 2 - Internal loopback + * 3 - External DQS + * [3:0] Frequency option + * 1 - 30MHz / 2 - 50MHz / 3 - 66MHz / 4 - 80MHz / 5 - 100MHz + * / 6 - 120MHz / 7 - 133MHz / 8 - 166MHz + * + * option[2] (Effective only if the bit[3:0] in option[0] > 1) + * [31:20] Reserved + * [19:16] IO voltage + * 0 - 3V / 1 - 1.8V + * [15:12] Pin group + * 0 - 1st group / 1 - 2nd group + * [11:8] Connection selection + * 0 - CA_CS0 / 1 - CB_CS0 / 2 - CA_CS0 + CB_CS0 + * (Two FLASH connected to CA and CB respectively) + * [7:0] Drive Strength + * 0 - Default value + * option[3] (Effective only if the bit[3:0] in option[0] > 2, + * required only for the QSPI NOR FLASH that not supports + * JESD216) + * [31:16] reserved + * [15:12] Sector Erase Command Option, not required here + * [11:8] Sector Size Option, not required here + * [7:0] Flash Size Option + * 0 - 4MB / 1 - 8MB / 2 - 16MB + */ +__attribute__ ((section(".nor_cfg_option"))) const uint32_t option[4] = { + 0xfcf90001, 0x00000007, 0x0, 0x0 + }; +uint32_t __fw_size__[] = {32768}; + +#endif diff --git a/boards/riscv/hpm6750evkmini/doc/img/hpm6750evkmini.png b/boards/riscv/hpm6750evkmini/doc/img/hpm6750evkmini.png new file mode 100644 index 000000000000..5bb39c9bbb45 Binary files /dev/null and b/boards/riscv/hpm6750evkmini/doc/img/hpm6750evkmini.png differ diff --git a/boards/riscv/hpm6750evkmini/doc/index.rst b/boards/riscv/hpm6750evkmini/doc/index.rst new file mode 100644 index 000000000000..92b7e71e9ad6 --- /dev/null +++ b/boards/riscv/hpm6750evkmini/doc/index.rst @@ -0,0 +1,160 @@ +.. _hpm6750evkmini: + +HPMicro HPM6750EVKMINI +###################### + +Overview +******** + +The HPM6750 is a dual-core flashless MCU running 816Mhz. +It has a 2MB continuous on-chip ram. +Also, it provides various memory interfaces, including SDRAM, Quad SPI NOR Flash, SD/eMMC. + +The figure shows the HPM6750EVKMINI board. + +.. image:: img/hpm6750evkmini.png + :align: center + :alt: HPM6750EVKMINI + +Hardware +******** + +The HPM6750EVKMINI platform integrates 2 cores 32-bit 816MHz RISC-V CPUs, DSP, +2MB RAM, Cache, SPI flash memory, ethernet controller and other peripherals. + +- HPM6750IVM MCU (816Mhz, 2MB OCRAM) +- Onboard Memory + - 128Mb SDRAM + - 64Mb Quad SPI NOR Flash +- Display & Camera + - LCD connector + - Camera (DVP) +- WiFi + - RW007 over SPI +- USB + - USB type C (USB 2.0 OTG) connector x2 +- Audio + - Mic + - DAO +- Others + - TF Slot + - FT2232 + - Beeper + - RGB LED +- Expansion port + - ART-PI extension port + +For more information about the HPMICRO SoC and HPM6750EVKMINI board: + +- `HPMICRO Design Resources`_ + +Supported Features +================== + +The Zephyr hpm6750evkmini board configuration supports the following hardware +features: + ++------------------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++==================+============+=====================================+ +| PLIC | on-chip | interrupt_controller | ++------------------+------------+-------------------------------------+ +| RISC-V Machine | on-chip | timer | +| Timer | | | ++------------------+------------+-------------------------------------+ +| Clock Controller | on-chip | clock_controller | ++------------------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++------------------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++------------------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++------------------+------------+-------------------------------------+ + +Connections and IOs +=================== + +.. rst-class:: rst-columns + +- UART0_RX : Y7 +- UART0_TX : Y6 +- LED_R : B19 +- LED_G : B18 +- LED_B : B20 + +System Clock +============ + +HPM6750EVKMINI System Clock is use the PLL clock driven by +external 24MHZ oscillator, By default System clock is 1GHz. + +Serial Port +=========== + +The HPM6750EVKMINI platform has 2 UARTs. +The Zephyr console output is by default assigned to UART0 and the default +settings are 115200 8N1. + +Programming and debugging +************************* + +Building +======== + +You can build applications in the usual way. Here is an example for +the :ref:`hello_world` application. + +.. zephyr-app-commands:: + :board: hpm6750evkmini + :zephyr-app: samples/hello_world + :goals: build + +Flashing +======== + +First, connect the hpm6750evkmini PWR DEBUG usb TypeC to your host +computer to prepare it for flashing. Then build and flash your application. + +If you want to use XIP mode (``CONFIG_XIP=y``). +If ``CONFIG_XIP=n``, you can load the program into RAM directly +and execute it. + +.. zephyr-app-commands:: + :board: hpm6750evkmini + :zephyr-app: samples/hello_world + :goals: flash + +Open a serial terminal with the following settings: + +.. code-block:: console + + $ minicom -D /dev/ + +- Speed: 115200 +- Data: 8 bits +- Parity: None +- Stop bits: 1 + +Replace with the port where the FT2232HL can be +found. For example, under Linux, /dev/ttyUSB1. + +you should see the following message in the terminal: + +.. code-block:: console + + Hello World! hpm6750evkmini + +Debugging +========= + +.. zephyr-app-commands:: + :board: hpm6750evkmini + :zephyr-app: samples/hello_world + :goals: debug + +References +========== + +.. _HPMICRO Design Resources: + http://www.hpmicro.com/resources/resources.html diff --git a/boards/riscv/hpm6750evkmini/hpm6750evkmini-pinctrl.dtsi b/boards/riscv/hpm6750evkmini/hpm6750evkmini-pinctrl.dtsi new file mode 100644 index 000000000000..4eb6647ab73a --- /dev/null +++ b/boards/riscv/hpm6750evkmini/hpm6750evkmini-pinctrl.dtsi @@ -0,0 +1,18 @@ +/* + * Copyright (c) 2022 HPMicro + * SPDX-License-Identifier: Apache-2.0 + */ +#include +&pinctrl { + pinmux_uart0: pinmux_uart0 { + group0 { + pinmux = + , + , + , + ; + drive-strength = "r000"; + power-source = "3v3"; + }; + }; +}; diff --git a/boards/riscv/hpm6750evkmini/hpm6750evkmini.dts b/boards/riscv/hpm6750evkmini/hpm6750evkmini.dts new file mode 100644 index 000000000000..2507b377634b --- /dev/null +++ b/boards/riscv/hpm6750evkmini/hpm6750evkmini.dts @@ -0,0 +1,129 @@ +/* + * Copyright (c) 2022 HPMicro + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include "hpm6750evkmini-pinctrl.dtsi" +#include + +/ { + model = "HPMicro HPM6750EVKMINI"; + compatible = "HPMicro,hpm6750evkmini"; + + chosen { + zephyr,console = &uart0; + zephyr,shell-uart = &uart0; + zephyr,sram = &sram; + zephyr,itcm = &ilm; + zephyr,dtcm = &dlm; + zephyr,flash = &flash0; + zephyr,code-partition = &slot0_partition; + }; + + dram: memory@40000000 { + device_type = "memory"; + reg = <0x40000000 DT_SIZE_M(16)>; + }; + + leds { + compatible = "gpio-leds"; + led_r: led_r { + gpios = <&gpiob 19 GPIO_ACTIVE_LOW>; + label = "LEDR"; + }; + led_g: led_g { + gpios = <&gpiob 18 GPIO_ACTIVE_LOW>; + label = "LEDG"; + }; + led_b: led_b { + gpios = <&gpiob 20 GPIO_ACTIVE_LOW>; + label = "LEDB"; + }; + }; + + gpio_keys { + compatible = "gpio-keys"; + wbutn: button_1 { + label = "Key"; + gpios = <&gpiod 20 GPIO_ACTIVE_LOW>; + zephyr,code = ; + }; + + pbutn: button_2 { + label = "Key"; + gpios = <&gpioz 2 GPIO_ACTIVE_LOW>; + zephyr,code = ; + }; + }; + + aliases { + led0 = &led_r; + led1 = &led_g; + led2 = &led_b; + sw0 = &wbutn; + }; +}; + +&gpio0 { + + gpiob: gpio@1 { + compatible = "hpmicro,hpm-gpio"; + reg = <0x0 0x4000>; + gpio-controller; + #gpio-cells = <2>; + hpmicro-gpio-port = <1>; + interrupts = <2 1>; + interrupt-parent = <&plic0>; + status = "okay"; + }; + + gpiod: gpio@3 { + compatible = "hpmicro,hpm-gpio"; + reg = <0x0 0x4000>; + gpio-controller; + #gpio-cells = <2>; + hpmicro-gpio-port = <3>; + interrupts = <4 1>; + interrupt-parent = <&plic0>; + status = "okay"; + }; + + gpioz: gpio@8 { + compatible = "hpmicro,hpm-gpio"; + reg = <0x00 0x4000>; + gpio-controller; + #gpio-cells = <2>; + hpmicro-gpio-port = <15>; + interrupts = <9 1>; + interrupt-parent = <&plic0>; + }; +}; + +&uart0 { + status = "okay"; + current-speed = <115200>; + pinctrl-0 = <&pinmux_uart0>; + pinctrl-names = "default"; +}; + +&flash0 { + status = "okay"; + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + boot_partition: partition@0 { + label = "mcuboot"; + reg = <0x0 0x3000>; + }; + + slot0_partition: partition@3000 { + label = "image-0"; + reg = <0x3000 DT_SIZE_M(4)>; + }; + }; +}; diff --git a/boards/riscv/hpm6750evkmini/hpm6750evkmini.yaml b/boards/riscv/hpm6750evkmini/hpm6750evkmini.yaml new file mode 100644 index 000000000000..01bdf205444c --- /dev/null +++ b/boards/riscv/hpm6750evkmini/hpm6750evkmini.yaml @@ -0,0 +1,18 @@ +# Copyright (c) 2022 HPMicro +# SPDX-License-Identifier: Apache-2.0 + +identifier: hpm6750evkmini +name: HPMicro HPM6750EVKMINI +type: mcu +arch: riscv32 +toolchain: + - zephyr + - cross-compile +ram: 2048 +supported: + - gpio + - uart +testing: + ignore_tags: + - bluetooth +vendor: hpmicro diff --git a/boards/riscv/hpm6750evkmini/hpm6750evkmini_defconfig b/boards/riscv/hpm6750evkmini/hpm6750evkmini_defconfig new file mode 100644 index 000000000000..925d339d23f7 --- /dev/null +++ b/boards/riscv/hpm6750evkmini/hpm6750evkmini_defconfig @@ -0,0 +1,25 @@ +CONFIG_SOC_SERIES_ANDES_HPMICRO=y +CONFIG_SOC_SERIES_HPM67XX_64XX=y +CONFIG_SOC_HPM675X=y +CONFIG_BOARD_HPM6750EVKMINI=y +CONFIG_XIP=n +CONFIG_PLIC=y +CONFIG_RISCV_MACHINE_TIMER=y +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_PINCTRL=y +CONFIG_BUILD_OUTPUT_HEX=y +CONFIG_CLOCK_CONTROL=y + +# Serial driver options +CONFIG_SERIAL=y +CONFIG_UART_INTERRUPT_DRIVEN=y + +# GPIO driver options +CONFIG_GPIO=y + +# HW DSP options +#CONFIG_SOC_ANDES_V5_HWDSP=y + +# not support hardware info +CONFIG_HWINFO_ANDES=n diff --git a/boards/riscv/hpm6750evkmini/pre_dt_board.cmake b/boards/riscv/hpm6750evkmini/pre_dt_board.cmake new file mode 100644 index 000000000000..9c994ae30303 --- /dev/null +++ b/boards/riscv/hpm6750evkmini/pre_dt_board.cmake @@ -0,0 +1,5 @@ +# Copyright (c) 2022, hpmicro +# SPDX-License-Identifier: Apache-2.0 + +# Suppress "simple_bus_reg" on HPMicro boards as all GPIO ports use the same register. +list(APPEND EXTRA_DTC_FLAGS "-Wno-simple_bus_reg") diff --git a/boards/riscv/hpm6750evkmini/support/boards/hpm6750evkmini.cfg b/boards/riscv/hpm6750evkmini/support/boards/hpm6750evkmini.cfg new file mode 100644 index 000000000000..82c8a02827b2 --- /dev/null +++ b/boards/riscv/hpm6750evkmini/support/boards/hpm6750evkmini.cfg @@ -0,0 +1,299 @@ +# Copyright (c) 2022 HPMicro +# SPDX-License-Identifier: Apache-2.0 + +# openocd flash driver argument: +# - ARG7: +# [31:28] Flash probe type +# 0 - SFDP SDR / 1 - SFDP DDR +# 2 - 1-4-4 Read (0xEB, 24-bit address) / 3 - 1-2-2 Read(0xBB, 24-bit address) +# 4 - HyperFLASH 1.8V / 5 - HyperFLASH 3V +# 6 - OctaBus DDR (SPI -> OPI DDR) +# 8 - Xccela DDR (SPI -> OPI DDR) +# 10 - EcoXiP DDR (SPI -> OPI DDR) +# [27:24] Command Pads after Power-on Reset +# 0 - SPI / 1 - DPI / 2 - QPI / 3 - OPI +# [23:20] Command Pads after Configuring FLASH +# 0 - SPI / 1 - DPI / 2 - QPI / 3 - OPI +# [19:16] Quad Enable Sequence (for the device support SFDP 1.0 only) +# 0 - Not needed +# 1 - QE bit is at bit 6 in Status Register 1 +# 2 - QE bit is at bit1 in Status Register 2 +# 3 - QE bit is at bit7 in Status Register 2 +# 4 - QE bit is at bit1 in Status Register 2 and should be programmed by 0x31 +# [15:8] Dummy cycles +# 0 - Auto-probed / detected / default value +# Others - User specified value, for DDR read, the dummy cycles should be 2 * cycles on FLASH datasheet +# [7:4] Misc. +# 0 - Not used +# 1 - SPI mode +# 2 - Internal loopback +# 3 - External DQS +# [3:0] Frequency option +# 1 - 30MHz / 2 - 50MHz / 3 - 66MHz / 4 - 80MHz / 5 - 100MHz / 6 - 120MHz / 7 - 133MHz / 8 - 166MHz +# - ARG8: +# [31:20] Reserved +# [19:16] IO voltage +# 0 - 3V / 1 - 1.8V +# [15:12] Pin group +# 0 - 1st group / 1 - 2nd group +# [11:8] Connection selection +# 0 - CA_CS0 / 1 - CB_CS0 / 2 - CA_CS0 + CB_CS0 (Two FLASH connected to CA and CB respectively) +# [7:0] Drive Strength +# 0 - Default value + +# xpi0 configs +# - flash driver: hpm_xpi +# - flash ctrl index: 0xF3040000 +# - base address: 0x80000000 +# - flash size: 0x1000000 +# - flash option0: 0x7 +flash bank xpi0 hpm_xpi 0x80000000 0x1000000 1 1 $_TARGET0 0xF3040000 0x7 + +proc init_clock {} { + $::_TARGET0 riscv dmi_write 0x39 0xF4002000 + $::_TARGET0 riscv dmi_write 0x3C 0x1 + + $::_TARGET0 riscv dmi_write 0x39 0xF4002000 + $::_TARGET0 riscv dmi_write 0x3C 0x2 + + $::_TARGET0 riscv dmi_write 0x39 0xF4000800 + $::_TARGET0 riscv dmi_write 0x3C 0xFFFFFFFF + + $::_TARGET0 riscv dmi_write 0x39 0xF4000810 + $::_TARGET0 riscv dmi_write 0x3C 0xFFFFFFFF + + $::_TARGET0 riscv dmi_write 0x39 0xF4000820 + $::_TARGET0 riscv dmi_write 0x3C 0xFFFFFFFF + + $::_TARGET0 riscv dmi_write 0x39 0xF4000830 + $::_TARGET0 riscv dmi_write 0x3C 0xFFFFFFFF + echo "clocks has been enabled!" +} + +proc init_sdram { } { +# configure dram frequency +# 133Mhz pll1_clk0: 266Mhz divide by 2 + #$::_TARGET0 riscv dmi_write 0x39 0xF4001820 + $::_TARGET0 riscv dmi_write 0x3C 0x201 +# 166Mhz pll2_clk0: 333Mhz divide by 2 + $::_TARGET0 riscv dmi_write 0x39 0xF4001820 + $::_TARGET0 riscv dmi_write 0x3C 0x401 + + # PD13 + $::_TARGET0 riscv dmi_write 0x39 0xF4040368 + $::_TARGET0 riscv dmi_write 0x3C 0xC + # PD12 + $::_TARGET0 riscv dmi_write 0x39 0xF4040360 + $::_TARGET0 riscv dmi_write 0x3C 0xC + # PD10 + $::_TARGET0 riscv dmi_write 0x39 0xF4040350 + $::_TARGET0 riscv dmi_write 0x3C 0xC + # PD09 + $::_TARGET0 riscv dmi_write 0x39 0xF4040348 + $::_TARGET0 riscv dmi_write 0x3C 0xC + # PD08 + $::_TARGET0 riscv dmi_write 0x39 0xF4040340 + $::_TARGET0 riscv dmi_write 0x3C 0xC + # PD07 + $::_TARGET0 riscv dmi_write 0x39 0xF4040338 + $::_TARGET0 riscv dmi_write 0x3C 0xC + # PD06 + $::_TARGET0 riscv dmi_write 0x39 0xF4040330 + $::_TARGET0 riscv dmi_write 0x3C 0xC + # PD05 + $::_TARGET0 riscv dmi_write 0x39 0xF4040328 + $::_TARGET0 riscv dmi_write 0x3C 0xC + # PD04 + $::_TARGET0 riscv dmi_write 0x39 0xF4040320 + $::_TARGET0 riscv dmi_write 0x3C 0xC + # PD03 + $::_TARGET0 riscv dmi_write 0x39 0xF4040318 + $::_TARGET0 riscv dmi_write 0x3C 0xC + # PD02 + $::_TARGET0 riscv dmi_write 0x39 0xF4040310 + $::_TARGET0 riscv dmi_write 0x3C 0xC + # PD01 + $::_TARGET0 riscv dmi_write 0x39 0xF4040308 + $::_TARGET0 riscv dmi_write 0x3C 0xC + # PD00 + $::_TARGET0 riscv dmi_write 0x39 0xF4040300 + $::_TARGET0 riscv dmi_write 0x3C 0xC + # PC29 + $::_TARGET0 riscv dmi_write 0x39 0xF40402E8 + $::_TARGET0 riscv dmi_write 0x3C 0xC + # PC28 + $::_TARGET0 riscv dmi_write 0x39 0xF40402E0 + $::_TARGET0 riscv dmi_write 0x3C 0xC + # PC27 + $::_TARGET0 riscv dmi_write 0x39 0xF40402D8 + $::_TARGET0 riscv dmi_write 0x3C 0xC + + # PC22 + $::_TARGET0 riscv dmi_write 0x39 0xF40402B0 + $::_TARGET0 riscv dmi_write 0x3C 0xC + # PC21 + $::_TARGET0 riscv dmi_write 0x39 0xF40402A8 + $::_TARGET0 riscv dmi_write 0x3C 0xC + # PC17 + $::_TARGET0 riscv dmi_write 0x39 0xF4040288 + $::_TARGET0 riscv dmi_write 0x3C 0xC + # PC15 + $::_TARGET0 riscv dmi_write 0x39 0xF4040278 + $::_TARGET0 riscv dmi_write 0x3C 0xC + # PC12 + $::_TARGET0 riscv dmi_write 0x39 0xF4040260 + $::_TARGET0 riscv dmi_write 0x3C 0xC + # PC11 + $::_TARGET0 riscv dmi_write 0x39 0xF4040258 + $::_TARGET0 riscv dmi_write 0x3C 0xC + # PC10 + $::_TARGET0 riscv dmi_write 0x39 0xF4040250 + $::_TARGET0 riscv dmi_write 0x3C 0xC + # PC09 + $::_TARGET0 riscv dmi_write 0x39 0xF4040248 + $::_TARGET0 riscv dmi_write 0x3C 0xC + # PC08 + $::_TARGET0 riscv dmi_write 0x39 0xF4040240 + $::_TARGET0 riscv dmi_write 0x3C 0xC + # PC07 + $::_TARGET0 riscv dmi_write 0x39 0xF4040238 + $::_TARGET0 riscv dmi_write 0x3C 0xC + # PC06 + $::_TARGET0 riscv dmi_write 0x39 0xF4040230 + $::_TARGET0 riscv dmi_write 0x3C 0xC + # PC05 + $::_TARGET0 riscv dmi_write 0x39 0xF4040228 + $::_TARGET0 riscv dmi_write 0x3C 0xC + # PC04 + $::_TARGET0 riscv dmi_write 0x39 0xF4040220 + $::_TARGET0 riscv dmi_write 0x3C 0xC + + # PC14 + $::_TARGET0 riscv dmi_write 0x39 0xF4040270 + $::_TARGET0 riscv dmi_write 0x3C 0xC + # PC13 + $::_TARGET0 riscv dmi_write 0x39 0xF4040268 + $::_TARGET0 riscv dmi_write 0x3C 0xC + # PC16 + # $::_TARGET0 riscv dmi_write 0x39 0xF4040280 + $::_TARGET0 riscv dmi_write 0x3C 0x1000C + # PC26 + $::_TARGET0 riscv dmi_write 0x39 0xF40402D0 + $::_TARGET0 riscv dmi_write 0x3C 0xC + # PC25 + $::_TARGET0 riscv dmi_write 0x39 0xF40402C8 + $::_TARGET0 riscv dmi_write 0x3C 0xC + # PC19 + $::_TARGET0 riscv dmi_write 0x39 0xF4040298 + $::_TARGET0 riscv dmi_write 0x3C 0xC + # PC18 + $::_TARGET0 riscv dmi_write 0x39 0xF4040290 + $::_TARGET0 riscv dmi_write 0x3C 0xC + # PC23 + $::_TARGET0 riscv dmi_write 0x39 0xF40402B8 + $::_TARGET0 riscv dmi_write 0x3C 0xC + # PC24 + $::_TARGET0 riscv dmi_write 0x39 0xF40402C0 + $::_TARGET0 riscv dmi_write 0x3C 0xC + # PC30 + $::_TARGET0 riscv dmi_write 0x39 0xF40402F0 + $::_TARGET0 riscv dmi_write 0x3C 0xC + # PC31 + $::_TARGET0 riscv dmi_write 0x39 0xF40402F8 + $::_TARGET0 riscv dmi_write 0x3C 0xC + # PC02 + $::_TARGET0 riscv dmi_write 0x39 0xF4040210 + $::_TARGET0 riscv dmi_write 0x3C 0xC + # PC03 + $::_TARGET0 riscv dmi_write 0x39 0xF4040218 + $::_TARGET0 riscv dmi_write 0x3C 0xC + + # dramc configuration + $::_TARGET0 riscv dmi_write 0x39 0xF3050000 + $::_TARGET0 riscv dmi_write 0x3C 0x1 + sleep 10 + $::_TARGET0 riscv dmi_write 0x39 0xF3050000 + $::_TARGET0 riscv dmi_write 0x3C 0x2 + $::_TARGET0 riscv dmi_write 0x39 0xF3050008 + $::_TARGET0 riscv dmi_write 0x3C 0x30524 + $::_TARGET0 riscv dmi_write 0x39 0xF305000C + $::_TARGET0 riscv dmi_write 0x3C 0x6030524 + $::_TARGET0 riscv dmi_write 0x39 0xF3050000 + $::_TARGET0 riscv dmi_write 0x3C 0x10000000 + + # 16MB + $::_TARGET0 riscv dmi_write 0x39 0xF3050010 + $::_TARGET0 riscv dmi_write 0x3C 0x40000019 + $::_TARGET0 riscv dmi_write 0x39 0xF3050014 + $::_TARGET0 riscv dmi_write 0x3C 0 + # 16-bit + $::_TARGET0 riscv dmi_write 0x39 0xF3050040 + $::_TARGET0 riscv dmi_write 0x3C 0xf31 + + # 133Mhz configuration + #$::_TARGET0 riscv dmi_write 0x39 0xF3050044 + $::_TARGET0 riscv dmi_write 0x3C 0x884e22 + # 166Mhz configuration + $::_TARGET0 riscv dmi_write 0x39 0xF3050044 + $::_TARGET0 riscv dmi_write 0x3C 0x884e33 + + $::_TARGET0 riscv dmi_write 0x39 0xF3050048 + $::_TARGET0 riscv dmi_write 0x3C 0x1020d0d + $::_TARGET0 riscv dmi_write 0x39 0xF3050048 + $::_TARGET0 riscv dmi_write 0x3C 0x1020d0d + $::_TARGET0 riscv dmi_write 0x39 0xF305004C + $::_TARGET0 riscv dmi_write 0x3C 0x2020300 + + # config delay cell + $::_TARGET0 riscv dmi_write 0x39 0xF3050150 + $::_TARGET0 riscv dmi_write 0x3C 0x3b + $::_TARGET0 riscv dmi_write 0x39 0xF3050150 + $::_TARGET0 riscv dmi_write 0x3C 0x203b + + $::_TARGET0 riscv dmi_write 0x39 0xF3050094 + $::_TARGET0 riscv dmi_write 0x3C 0 + $::_TARGET0 riscv dmi_write 0x39 0xF3050098 + $::_TARGET0 riscv dmi_write 0x3C 0 + + # precharge all + $::_TARGET0 riscv dmi_write 0x39 0xF3050090 + $::_TARGET0 riscv dmi_write 0x3C 0x40000000 + $::_TARGET0 riscv dmi_write 0x39 0xF305009C + $::_TARGET0 riscv dmi_write 0x3C 0xA55A000F + sleep 500 + $::_TARGET0 riscv dmi_write 0x39 0xF305003C + $::_TARGET0 riscv dmi_write 0x3C 0x3 + # auto refresh + $::_TARGET0 riscv dmi_write 0x39 0xF305009C + $::_TARGET0 riscv dmi_write 0x3C 0xA55A000C + sleep 500 + $::_TARGET0 riscv dmi_write 0x39 0xF305003C + $::_TARGET0 riscv dmi_write 0x3C 0x3 + $::_TARGET0 riscv dmi_write 0x39 0xF305009C + $::_TARGET0 riscv dmi_write 0x3C 0xA55A000C + sleep 500 + $::_TARGET0 riscv dmi_write 0x39 0xF305003C + $::_TARGET0 riscv dmi_write 0x3C 0x3 + + # set mode + $::_TARGET0 riscv dmi_write 0x39 0xF30500A0 + $::_TARGET0 riscv dmi_write 0x3C 0x33 + $::_TARGET0 riscv dmi_write 0x39 0xF305009C + $::_TARGET0 riscv dmi_write 0x3C 0xA55A000A + sleep 500 + $::_TARGET0 riscv dmi_write 0x39 0xF305003C + $::_TARGET0 riscv dmi_write 0x3C 0x3 + + $::_TARGET0 riscv dmi_write 0x39 0xF305004C + $::_TARGET0 riscv dmi_write 0x3C 0x2020301 + echo "SDRAM has been initialized" +} + +$_TARGET0 configure -event reset-init { + init_clock + init_sdram +} + +$_TARGET0 configure -event gdb-attach { + reset halt +} diff --git a/boards/riscv/hpm6750evkmini/support/probes/ft2232.cfg b/boards/riscv/hpm6750evkmini/support/probes/ft2232.cfg new file mode 100644 index 000000000000..4b1a661f08d6 --- /dev/null +++ b/boards/riscv/hpm6750evkmini/support/probes/ft2232.cfg @@ -0,0 +1,14 @@ +# Copyright (c) 2022 HPMicro +# SPDX-License-Identifier: Apache-2.0 + +bindto 0.0.0.0 +adapter speed 10000 +reset_config trst_and_srst +adapter srst delay 50 + +adapter driver ftdi +ftdi_vid_pid 0x0403 0x6010 + +ftdi_layout_init 0x0208 0x020b +ftdi_layout_signal nTRST -data 0x0200 -noe 0x0400 +ftdi_layout_signal nSRST -data 0x0100 -noe 0x0800 diff --git a/boards/riscv/hpm6750evkmini/support/soc/hpm6750-single-core.cfg b/boards/riscv/hpm6750evkmini/support/soc/hpm6750-single-core.cfg new file mode 100644 index 000000000000..0139f857e480 --- /dev/null +++ b/boards/riscv/hpm6750evkmini/support/soc/hpm6750-single-core.cfg @@ -0,0 +1,13 @@ +# Copyright (c) 2022 HPMicro +# SPDX-License-Identifier: Apache-2.0 + +set _CHIP hpm6750 +set _CPUTAPID 0x1000563D +jtag newtap $_CHIP cpu -irlen 5 -expected-id $_CPUTAPID + +set _TARGET0 $_CHIP.cpu0 +target create $_TARGET0 riscv -chain-position $_CHIP.cpu -coreid 0 + +$_TARGET0 configure -work-area-phys 0x00000000 -work-area-size 0x20000 -work-area-backup 0 + +targets $_TARGET0 diff --git a/dts/riscv/hpmicro/hpm6750.dtsi b/dts/riscv/hpmicro/hpm6750.dtsi index 34f9483d8fa1..753ddc018b2d 100644 --- a/dts/riscv/hpmicro/hpm6750.dtsi +++ b/dts/riscv/hpmicro/hpm6750.dtsi @@ -109,7 +109,7 @@ reg = <0xe4000000 0x04000000>; riscv,max-priority = <255>; riscv,ndev = <1023>; - interrupts-extended = <&CPU0_intc 0 &CPU1_intc 0>; + interrupts-extended = <&CPU0_intc 11 &CPU1_intc 11>; }; plic_sw0: interrupt-controller@e6400000 { diff --git a/soc/riscv/andes_v5/hpmicro/Kconfig.defconfig.series b/soc/riscv/andes_v5/hpmicro/Kconfig.defconfig.series index fcc2443038c1..6461a069d991 100644 --- a/soc/riscv/andes_v5/hpmicro/Kconfig.defconfig.series +++ b/soc/riscv/andes_v5/hpmicro/Kconfig.defconfig.series @@ -22,10 +22,10 @@ config TEST_EXTRA_STACK_SIZE default 2048 config 2ND_LVL_ISR_TBL_OFFSET - default 0 + default 12 config 2ND_LVL_INTR_00_OFFSET - default 0 + default 11 config MAX_IRQ_PER_AGGREGATOR default 112