From 9c5ef6b5e8304aa446a1d6c6e007c50166ed46b3 Mon Sep 17 00:00:00 2001 From: TOKITA Hiroshi Date: Thu, 12 Sep 2024 23:23:33 +0900 Subject: [PATCH] drivers: clock_control: renesas_ra: Adding macros to convert DT values Adding the macros `RA_CGC_CLK_SRC` and `RA_CGC_CLK_DIV` that derive the BSP clock settings from the DeviceTree node settings. I also define some aliases to fill in the gaps with the BSP naming conventions. Signed-off-by: TOKITA Hiroshi --- .../clock_control_renesas_ra_cgc.c | 9 +- .../drivers/clock_control/renesas_ra_cgc.h | 46 +++++++ include/zephyr/dt-bindings/clock/ra_clock.h | 130 ------------------ 3 files changed, 51 insertions(+), 134 deletions(-) diff --git a/drivers/clock_control/clock_control_renesas_ra_cgc.c b/drivers/clock_control/clock_control_renesas_ra_cgc.c index b03852fc86e1..33d2f3e82d27 100644 --- a/drivers/clock_control/clock_control_renesas_ra_cgc.c +++ b/drivers/clock_control/clock_control_renesas_ra_cgc.c @@ -90,10 +90,11 @@ static const struct clock_control_driver_api clock_control_reneas_ra_api = { #define INIT_PCLK(node_id) \ IF_ENABLED(DT_NODE_HAS_COMPAT(node_id, renesas_ra_cgc_pclk), \ (static const struct clock_control_ra_pclk_cfg node_id##_cfg = \ - {.clk_src = DT_PROP_OR(node_id, clk_src, \ - DT_PROP_OR(DT_PARENT(node_id), sysclock_src, \ - RA_CLOCK_SOURCE_DISABLE)), \ - .clk_div = DT_PROP_OR(node_id, clk_div, RA_SYS_CLOCK_DIV_1)}; \ + {.clk_src = COND_CODE_1( \ + DT_NODE_HAS_PROP(node_id, clocks), \ + (RA_CGC_CLK_SRC(DT_CLOCKS_CTLR(node_id))), \ + (RA_CGC_CLK_SRC(DT_CLOCKS_CTLR(DT_PARENT(node_id))))), \ + .clk_div = RA_CGC_CLK_DIV(node_id, div, 1)}; \ DEVICE_DT_DEFINE(node_id, &clock_control_ra_init_pclk, NULL, NULL, \ &node_id##_cfg, PRE_KERNEL_1, \ CONFIG_KERNEL_INIT_PRIORITY_OBJECTS, \ diff --git a/include/zephyr/drivers/clock_control/renesas_ra_cgc.h b/include/zephyr/drivers/clock_control/renesas_ra_cgc.h index 2e551256e850..a7f147382fdc 100644 --- a/include/zephyr/drivers/clock_control/renesas_ra_cgc.h +++ b/include/zephyr/drivers/clock_control/renesas_ra_cgc.h @@ -9,6 +9,52 @@ #include #include +#define RA_CGC_PROP_HAS_STATUS_OKAY_OR(node_id, prop, default_value) \ + COND_CODE_1(DT_NODE_HAS_STATUS(node_id, okay), (DT_PROP(node_id, prop)), (default_value)) + +#define RA_CGC_CLK_SRC(node_id) \ + COND_CODE_1(DT_NODE_HAS_STATUS(node_id, okay), \ + (UTIL_CAT(BSP_CLOCKS_SOURCE_, DT_NODE_FULL_NAME_UPPER_TOKEN(node_id))), \ + (BSP_CLOCKS_CLOCK_DISABLED)) + +#define RA_CGC_CLK_DIV(clk, prop, default_value) \ + UTIL_CAT(RA_CGC_DIV_, DT_NODE_FULL_NAME_UPPER_TOKEN(clk)) \ + (RA_CGC_PROP_HAS_STATUS_OKAY_OR(clk, prop, default_value)) + +#define RA_CGC_DIV_BCLK(n) UTIL_CAT(BSP_CLOCKS_SYS_CLOCK_DIV_, n) +#define RA_CGC_DIV_CANFDCLK(n) UTIL_CAT(BSP_CLOCKS_CANFD_CLOCK_DIV_, n) +#define RA_CGC_DIV_CECCLK(n) UTIL_CAT(BSP_CLOCKS_CEC_CLOCK_DIV_, n) +#define RA_CGC_DIV_CLKOUT(n) UTIL_CAT(BSP_CLOCKS_CLKOUT_DIV_, n) +#define RA_CGC_DIV_CPUCLK(n) UTIL_CAT(BSP_CLOCKS_SYS_CLOCK_DIV_, n) +#define RA_CGC_DIV_FCLK(n) UTIL_CAT(BSP_CLOCKS_SYS_CLOCK_DIV_, n) +#define RA_CGC_DIV_I3CCLK(n) UTIL_CAT(BSP_CLOCKS_I3C_CLOCK_DIV_, n) +#define RA_CGC_DIV_ICLK(n) UTIL_CAT(BSP_CLOCKS_SYS_CLOCK_DIV_, n) +#define RA_CGC_DIV_LCDCLK(n) UTIL_CAT(BSP_CLOCKS_LCD_CLOCK_DIV_, n) +#define RA_CGC_DIV_OCTASPICLK(n) UTIL_CAT(BSP_CLOCKS_OCTA_CLOCK_DIV_, n) +#define RA_CGC_DIV_PCLKA(n) UTIL_CAT(BSP_CLOCKS_SYS_CLOCK_DIV_, n) +#define RA_CGC_DIV_PCLKB(n) UTIL_CAT(BSP_CLOCKS_SYS_CLOCK_DIV_, n) +#define RA_CGC_DIV_PCLKC(n) UTIL_CAT(BSP_CLOCKS_SYS_CLOCK_DIV_, n) +#define RA_CGC_DIV_PCLKD(n) UTIL_CAT(BSP_CLOCKS_SYS_CLOCK_DIV_, n) +#define RA_CGC_DIV_PCLKE(n) UTIL_CAT(BSP_CLOCKS_SYS_CLOCK_DIV_, n) +#define RA_CGC_DIV_PLL(n) UTIL_CAT(BSP_CLOCKS_PLL_DIV_, n) +#define RA_CGC_DIV_PLL2(n) UTIL_CAT(BSP_CLOCKS_PLL_DIV_, n) +#define RA_CGC_DIV_SCICLK(n) UTIL_CAT(BSP_CLOCKS_SCI_CLOCK_DIV_, n) +#define RA_CGC_DIV_SPICLK(n) UTIL_CAT(BSP_CLOCKS_SPI_CLOCK_DIV_, n) +#define RA_CGC_DIV_U60CLK(n) UTIL_CAT(BSP_CLOCKS_USB60_CLOCK_DIV_, n) +#define RA_CGC_DIV_UCLK(n) UTIL_CAT(BSP_CLOCKS_USB_CLOCK_DIV_, n) + +#define BSP_CLOCKS_SOURCE_PLL BSP_CLOCKS_SOURCE_CLOCK_PLL +#define BSP_CLOCKS_SOURCE_PLL2 BSP_CLOCKS_SOURCE_CLOCK_PLL + +#define BSP_CLOCKS_CLKOUT_DIV_1 (0) +#define BSP_CLOCKS_CLKOUT_DIV_2 (1) +#define BSP_CLOCKS_CLKOUT_DIV_4 (2) +#define BSP_CLOCKS_CLKOUT_DIV_8 (3) +#define BSP_CLOCKS_CLKOUT_DIV_16 (4) +#define BSP_CLOCKS_CLKOUT_DIV_32 (5) +#define BSP_CLOCKS_CLKOUT_DIV_64 (6) +#define BSP_CLOCKS_CLKOUT_DIV_128 (7) + struct clock_control_ra_pclk_cfg { uint32_t clk_src; uint32_t clk_div; diff --git a/include/zephyr/dt-bindings/clock/ra_clock.h b/include/zephyr/dt-bindings/clock/ra_clock.h index d88b1b93646b..97fc2e41b560 100644 --- a/include/zephyr/dt-bindings/clock/ra_clock.h +++ b/include/zephyr/dt-bindings/clock/ra_clock.h @@ -7,136 +7,6 @@ #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_RA_H_ #define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_RA_H_ -#define RA_PLL_SOURCE_HOCO 0 -#define RA_PLL_SOURCE_MOCO 1 -#define RA_PLL_SOURCE_LOCO 2 -#define RA_PLL_SOURCE_MAIN_OSC 3 -#define RA_PLL_SOURCE_SUBCLOCK 4 -#define RA_PLL_SOURCE_DISABLE 0xff - -#define RA_CLOCK_SOURCE_HOCO 0 -#define RA_CLOCK_SOURCE_MOCO 1 -#define RA_CLOCK_SOURCE_LOCO 2 -#define RA_CLOCK_SOURCE_MAIN_OSC 3 -#define RA_CLOCK_SOURCE_SUBCLOCK 4 -#define RA_CLOCK_SOURCE_PLL 5 -#define RA_CLOCK_SOURCE_PLL1P RA_CLOCK_SOURCE_PLL -#define RA_CLOCK_SOURCE_PLL2 6 -#define RA_CLOCK_SOURCE_PLL2P RA_CLOCK_SOURCE_PLL2 -#define RA_CLOCK_SOURCE_PLL1Q 7 -#define RA_CLOCK_SOURCE_PLL1R 8 -#define RA_CLOCK_SOURCE_PLL2Q 9 -#define RA_CLOCK_SOURCE_PLL2R 10 -#define RA_CLOCK_SOURCE_DISABLE 0xff - -#define RA_SYS_CLOCK_DIV_1 0 -#define RA_SYS_CLOCK_DIV_2 1 -#define RA_SYS_CLOCK_DIV_4 2 -#define RA_SYS_CLOCK_DIV_8 3 -#define RA_SYS_CLOCK_DIV_16 4 -#define RA_SYS_CLOCK_DIV_32 5 -#define RA_SYS_CLOCK_DIV_64 6 -#define RA_SYS_CLOCK_DIV_128 7 /* available for CLKOUT only */ -#define RA_SYS_CLOCK_DIV_3 8 -#define RA_SYS_CLOCK_DIV_6 9 -#define RA_SYS_CLOCK_DIV_12 10 - -/* PLL divider options. */ -#define RA_PLL_DIV_1 0 -#define RA_PLL_DIV_2 1 -#define RA_PLL_DIV_3 2 -#define RA_PLL_DIV_4 3 -#define RA_PLL_DIV_5 4 -#define RA_PLL_DIV_6 5 -#define RA_PLL_DIV_8 7 -#define RA_PLL_DIV_9 8 -#define RA_PLL_DIV_16 15 - -/* USB clock divider options. */ -#define RA_USB_CLOCK_DIV_1 0 -#define RA_USB_CLOCK_DIV_2 1 -#define RA_USB_CLOCK_DIV_3 2 -#define RA_USB_CLOCK_DIV_4 3 -#define RA_USB_CLOCK_DIV_5 4 -#define RA_USB_CLOCK_DIV_6 5 -#define RA_USB_CLOCK_DIV_8 7 - -/* USB60 clock divider options. */ -#define RA_USB60_CLOCK_DIV_1 0 -#define RA_USB60_CLOCK_DIV_2 1 -#define RA_USB60_CLOCK_DIV_3 5 -#define RA_USB60_CLOCK_DIV_4 2 -#define RA_USB60_CLOCK_DIV_5 6 -#define RA_USB60_CLOCK_DIV_6 3 -#define RA_USB60_CLOCK_DIV_8 4 - -/* OCTA clock divider options. */ -#define RA_OCTA_CLOCK_DIV_1 0 -#define RA_OCTA_CLOCK_DIV_2 1 -#define RA_OCTA_CLOCK_DIV_4 2 -#define RA_OCTA_CLOCK_DIV_6 3 -#define RA_OCTA_CLOCK_DIV_8 4 - -/* CANFD clock divider options. */ -#define RA_CANFD_CLOCK_DIV_1 0 -#define RA_CANFD_CLOCK_DIV_2 1 -#define RA_CANFD_CLOCK_DIV_3 5 -#define RA_CANFD_CLOCK_DIV_4 2 -#define RA_CANFD_CLOCK_DIV_5 6 -#define RA_CANFD_CLOCK_DIV_6 3 -#define RA_CANFD_CLOCK_DIV_8 4 - -/* SCI clock divider options. */ -#define RA_SCI_CLOCK_DIV_1 0 -#define RA_SCI_CLOCK_DIV_2 1 -#define RA_SCI_CLOCK_DIV_3 5 -#define RA_SCI_CLOCK_DIV_4 2 -#define RA_SCI_CLOCK_DIV_5 6 -#define RA_SCI_CLOCK_DIV_6 3 -#define RA_SCI_CLOCK_DIV_8 4 - -/* SPI clock divider options. */ -#define RA_SPI_CLOCK_DIV_1 0 -#define RA_SPI_CLOCK_DIV_2 1 -#define RA_SPI_CLOCK_DIV_3 5 -#define RA_SPI_CLOCK_DIV_4 2 -#define RA_SPI_CLOCK_DIV_5 6 -#define RA_SPI_CLOCK_DIV_6 3 -#define RA_SPI_CLOCK_DIV_8 4 - -/* CEC clock divider options. */ -#define RA_CEC_CLOCK_DIV_1 0 -#define RA_CEC_CLOCK_DIV_2 1 - -/* I3C clock divider options. */ -#define RA_I3C_CLOCK_DIV_1 0 -#define RA_I3C_CLOCK_DIV_2 1 -#define RA_I3C_CLOCK_DIV_3 5 -#define RA_I3C_CLOCK_DIV_4 2 -#define RA_I3C_CLOCK_DIV_5 6 -#define RA_I3C_CLOCK_DIV_6 3 -#define RA_I3C_CLOCK_DIV_8 4 - -/* LCD clock divider options. */ -#define RA_LCD_CLOCK_DIV_1 0 -#define RA_LCD_CLOCK_DIV_2 1 -#define RA_LCD_CLOCK_DIV_3 5 -#define RA_LCD_CLOCK_DIV_4 2 -#define RA_LCD_CLOCK_DIV_5 6 -#define RA_LCD_CLOCK_DIV_6 3 -#define RA_LCD_CLOCK_DIV_8 4 - -/* SDADC clock divider options. */ -#define RA_SDADC_CLOCK_DIV_1 0 -#define RA_SDADC_CLOCK_DIV_2 1 -#define RA_SDADC_CLOCK_DIV_3 2 -#define RA_SDADC_CLOCK_DIV_4 3 -#define RA_SDADC_CLOCK_DIV_5 4 -#define RA_SDADC_CLOCK_DIV_6 5 -#define RA_SDADC_CLOCK_DIV_8 6 -#define RA_SDADC_CLOCK_DIV_12 7 -#define RA_SDADC_CLOCK_DIV_16 8 - #define MSTPA 0 #define MSTPB 1 #define MSTPC 2