diff --git a/s32/drivers/s32ze/BaseNXP/header/S32Z2_PSI5.h b/s32/drivers/s32ze/BaseNXP/header/S32Z2_PSI5.h index 1dcf393a3..133da053f 100644 --- a/s32/drivers/s32ze/BaseNXP/header/S32Z2_PSI5.h +++ b/s32/drivers/s32ze/BaseNXP/header/S32Z2_PSI5.h @@ -72,7 +72,7 @@ #define PSI5_CHANNEL_CH_PMR_COUNT 32u #define PSI5_CHANNEL_CH_SFR_COUNT 6u #define PSI5_CHANNEL_CH_SFCR_COUNT 6u -#define PSI5_CHANNEL_COUNT 4u +#define PSI5_CHANNEL_COUNT 4 /** PSI5 - Register Layout Typedef */ typedef struct { @@ -132,7 +132,7 @@ typedef struct { } PSI5_Type, *PSI5_MemMapPtr; /** Number of instances of the PSI5 module. */ -#define PSI5_INSTANCE_COUNT (2u) +#define PSI5_INSTANCE_COUNT 2 /* PSI5 - Peripheral instance base addresses */ /** Peripheral PSI5_0 base address */ diff --git a/s32/drivers/s32ze/BaseNXP/include/Psi5_MemMap.h b/s32/drivers/s32ze/BaseNXP/include/Psi5_MemMap.h new file mode 100644 index 000000000..7fbbf83b9 --- /dev/null +++ b/s32/drivers/s32ze/BaseNXP/include/Psi5_MemMap.h @@ -0,0 +1,5 @@ +/* + * Copyright 2024 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + */ diff --git a/s32/drivers/s32ze/CMakeLists.txt b/s32/drivers/s32ze/CMakeLists.txt index 7a38f9544..0e6b8b5c6 100644 --- a/s32/drivers/s32ze/CMakeLists.txt +++ b/s32/drivers/s32ze/CMakeLists.txt @@ -15,4 +15,5 @@ if (CONFIG_ETH_NXP_S32_NETC) endif() add_subdirectory_ifdef(CONFIG_CAN_NXP_S32_CANXL Can_CANEXCEL) add_subdirectory_ifdef(CONFIG_NXP_S32_EMIOS Mcl) -add_subdirectory_ifdef(CONFIG_PWM_NXP_S32_EMIOS Pwm) \ No newline at end of file +add_subdirectory_ifdef(CONFIG_PWM_NXP_S32_EMIOS Pwm) +add_subdirectory_ifdef(CONFIG_PSI5_NXP_S32 Psi5) diff --git a/s32/drivers/s32ze/Psi5/CMakeLists.txt b/s32/drivers/s32ze/Psi5/CMakeLists.txt new file mode 100644 index 000000000..cdb9b2314 --- /dev/null +++ b/s32/drivers/s32ze/Psi5/CMakeLists.txt @@ -0,0 +1,6 @@ +# Copyright 2024 NXP +# SPDX-License-Identifier: BSD-3-Clause + +zephyr_include_directories(include) +zephyr_library_sources(src/Psi5_Ip.c) +zephyr_library_sources(src/Psi5_Ip_Irq.c) diff --git a/s32/drivers/s32ze/Psi5/include/Psi5_Ip.h b/s32/drivers/s32ze/Psi5/include/Psi5_Ip.h new file mode 100644 index 000000000..eca979a6f --- /dev/null +++ b/s32/drivers/s32ze/Psi5/include/Psi5_Ip.h @@ -0,0 +1,247 @@ +/* + * Copyright 2021-2024 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef PSI5_IP_H +#define PSI5_IP_H + +#if defined(__cplusplus) +extern "C" { +#endif + + +/*================================================================================================== +* INCLUDE FILES +* 1) system and project includes +* 2) needed interfaces from external units +* 3) internal and external interfaces from this unit +==================================================================================================*/ +#include "Psi5_Ip_Types.h" +#include "Psi5_Ip_Cfg.h" + +/*================================================================================================== +* SOURCE FILE VERSION INFOPSI5ATION +==================================================================================================*/ +#define PSI5_IP_VENDOR_ID 43 +#define PSI5_IP_AR_RELEASE_MAJOR_VERSION 4 +#define PSI5_IP_AR_RELEASE_MINOR_VERSION 7 +#define PSI5_IP_AR_RELEASE_REVISION_VERSION 0 +#define PSI5_IP_SW_MAJOR_VERSION 2 +#define PSI5_IP_SW_MINOR_VERSION 0 +#define PSI5_IP_SW_PATCH_VERSION 0 + + +/*================================================================================================== +* FILE VERSION CHECKS +==================================================================================================*/ +/* Checks against Psi5_Ip_Types.h */ +#if (PSI5_IP_VENDOR_ID != PSI5_IP_TYPES_VENDOR_ID) + #error "Psi5_Ip.h and Psi5_Ip_Types.h have different vendor ids" +#endif +#if ((PSI5_IP_AR_RELEASE_MAJOR_VERSION != PSI5_IP_TYPES_AR_RELEASE_MAJOR_VERSION) || \ + (PSI5_IP_AR_RELEASE_MINOR_VERSION != PSI5_IP_TYPES_AR_RELEASE_MINOR_VERSION) || \ + (PSI5_IP_AR_RELEASE_REVISION_VERSION != PSI5_IP_TYPES_AR_RELEASE_REVISION_VERSION) \ + ) + #error "AUTOSAR Version Numbers of Psi5_Ip.h and Psi5_Ip_Types.h are different" +#endif +#if ((PSI5_IP_SW_MAJOR_VERSION != PSI5_IP_TYPES_SW_MAJOR_VERSION) || \ + (PSI5_IP_SW_MINOR_VERSION != PSI5_IP_TYPES_SW_MINOR_VERSION) || \ + (PSI5_IP_SW_PATCH_VERSION != PSI5_IP_TYPES_SW_PATCH_VERSION) \ + ) + #error "Software Version Numbers of Psi5_Ip.h and Psi5_Ip_Types.h are different" +#endif + +/* Checks against Psi5_Ip_Cfg.h */ +#if (PSI5_IP_VENDOR_ID != PSI5_IP_CFG_VENDOR_ID) + #error "Psi5_Ip.h and Psi5_Ip_Cfg.h have different vendor ids" +#endif +#if ((PSI5_IP_AR_RELEASE_MAJOR_VERSION != PSI5_IP_CFG_AR_RELEASE_MAJOR_VERSION) || \ + (PSI5_IP_AR_RELEASE_MINOR_VERSION != PSI5_IP_CFG_AR_RELEASE_MINOR_VERSION) || \ + (PSI5_IP_AR_RELEASE_REVISION_VERSION != PSI5_IP_CFG_AR_RELEASE_REVISION_VERSION) \ + ) + #error "AUTOSAR Version Numbers of Psi5_Ip.h and Psi5_Ip_Cfg.h are different" +#endif +#if ((PSI5_IP_SW_MAJOR_VERSION != PSI5_IP_CFG_SW_MAJOR_VERSION) || \ + (PSI5_IP_SW_MINOR_VERSION != PSI5_IP_CFG_SW_MINOR_VERSION) || \ + (PSI5_IP_SW_PATCH_VERSION != PSI5_IP_CFG_SW_PATCH_VERSION) \ + ) + #error "Software Version Numbers of Psi5_Ip.h and Psi5_Ip_Cfg.h are different" +#endif + +/*================================================================================================== +* CONSTANTS +==================================================================================================*/ + +/*================================================================================================== +* DEFINES AND MACROS +==================================================================================================*/ + +/*================================================================================================== +* ENUMS +==================================================================================================*/ + +/*================================================================================================== +* STRUCTURES AND OTHER TYPEDEFS +==================================================================================================*/ + +/*================================================================================================== +* GLOBAL VARIABLE DECLARATIONS +==================================================================================================*/ + +/*================================================================================================== +* FUNCTION PROTOTYPES +==================================================================================================*/ + +#define PSI5_START_SEC_CONFIG_DATA_UNSPECIFIED +#include "Psi5_MemMap.h" +/** +* @brief Export PSI5 configurations. +*/ +PSI5_IP_CONFIG_EXT + +#define PSI5_STOP_SEC_CONFIG_DATA_UNSPECIFIED +#include "Psi5_MemMap.h" + +#define PSI5_START_SEC_CODE +#include "Psi5_MemMap.h" + + +/** +* @brief Interrupt handler signature for PSI5 module. +* +* @param[in] Psi5InstanceId Instance number +* @param[in] Psi5ChannelId Instance channel number +* @return void +* +*/ +void Psi5_Ip_IRQ_Handler(const Psi5_Ip_InstanceIdType Psi5InstanceId, + const Psi5_Ip_HwChannelIdType Psi5ChannelId + ); +/*! + * @brief Main initializer for the driver + * + * Initializes the driver for a given peripheral + * according to the given configuration structure. + * + * @param[in] configPtr Pointer to the configuration structure + */ +void Psi5_Ip_Init(const Psi5_Ip_ConfigType *configPtr); + +/*! + * @brief Reset the peripheral. + * + * De-Initializes the peripheral and brings it's registers into a reset state. + * + */ +void Psi5_Ip_DeInit(void); + +#if (STD_ON == PSI5_IP_TRANSMIT_API) +/*! + * @brief Transmit a data frame + * + * Transmits a data frame according to configuration. + * + * @param[in] Psi5InstanceId Instance number + * @param[in] Psi5ChannelId Channel number + * @param[in] Psi5Data Data to send + * @return STATUS_SUCCESS If transmit succeeded + * @return STATUS_ERROR If not configured or not enabled or not ready + */ +Std_ReturnType Psi5_Ip_Transmit(const Psi5_Ip_InstanceIdType Psi5InstanceId, + const Psi5_Ip_HwChannelIdType Psi5ChannelId, + const uint64 Psi5Data + ); +#endif + +#if (STD_ON == PSI5_IP_GET_TRANSMISSION_STATUS_API) +/*! + * @brief Transmission status + * + * Returns the status of the transmission. + * + * @param[in] Psi5InstanceId Instance number + * @param[in] Psi5ChannelId Channel number + * @return true If transmission ready + * @return false If transmission pending + */ +boolean Psi5_Ip_GetTransmissionStatus(const Psi5_Ip_InstanceIdType Psi5InstanceId, + const Psi5_Ip_HwChannelIdType Psi5ChannelId + ); +#endif + +#if (STD_ON == PSI5_IP_GET_PSI5_FRAME_API) +/*! + * @brief Gets a PSI5 frame + * + * Returns the last received PSI5 frame. + * + * @param[in] Psi5InstanceId Instance number + * @param[in] Psi5ChannelId Channel number + * @param[out] Psi5FramePtr Target variable + */ +Std_ReturnType Psi5_Ip_GetPsi5Frame(const Psi5_Ip_InstanceIdType Psi5InstanceId, + const Psi5_Ip_HwChannelIdType Psi5ChannelId, + Psi5_Ip_Psi5FrameType *PsiFramePtr + ); +#endif + +#if (STD_ON == PSI5_IP_GET_SMC_FRAME_API) +/*! + * @brief Gets a SMC frame + * + * Returns the last received SMC frame. + * + * @param[in] Psi5InstanceId Instance number + * @param[in] Psi5ChannelId Channel number + * @param[out] Psi5FramePtr Target variable + */ +Std_ReturnType Psi5_Ip_GetSmcFrame(const Psi5_Ip_InstanceIdType Psi5InstanceId, + const Psi5_Ip_HwChannelIdType Psi5ChannelId, + Psi5_Ip_SmcFrameType *Psi5SmcFramePtr + ); +#endif + +#if (STD_ON == PSI5_IP_SET_GLOBAL_SYNC_API) +/*! + * @brief Global sync state + * + * Changes the global sync pulse generator state + * + * @param[in] Psi5InstanceId Instance number + * @param[in] Psi5State Desired state + */ +Std_ReturnType Psi5_Ip_SetGlobalSync(const uint8 Psi5InstanceId, + const boolean PsiState + ); +#endif + +#if (STD_ON == PSI5_IP_SET_CHANNEL_SYNC_API) +/*! + * @brief Channel sync state + * + * Changes the channel sync pulse generator state + * + * @param[in] Psi5InstanceId Instance number + * @param[in] Psi5ChannelId Instance channel number + * @param[in] Psi5State Desired state + */ +Std_ReturnType Psi5_Ip_SetChannelSync(const Psi5_Ip_InstanceIdType Psi5InstanceId, + const Psi5_Ip_HwChannelIdType Psi5ChannelId, + const boolean PsiState + ); +#endif + +#define PSI5_STOP_SEC_CODE +#include "Psi5_MemMap.h" + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +/*! @}*/ /* End of addtogroup psi5 */ + +#endif /* PSI5_IP_H */ diff --git a/s32/drivers/s32ze/Psi5/include/Psi5_Ip_Irq.h b/s32/drivers/s32ze/Psi5/include/Psi5_Ip_Irq.h new file mode 100644 index 000000000..bc8872cee --- /dev/null +++ b/s32/drivers/s32ze/Psi5/include/Psi5_Ip_Irq.h @@ -0,0 +1,174 @@ +/* + * Copyright 2021-2024 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef PSI5_IP_IRQ_H +#define PSI5_IP_IRQ_H + +#if defined(__cplusplus) +extern "C" { +#endif + + +/*================================================================================================== +* INCLUDE FILES +* 1) system and project includes +* 2) needed interfaces from external units +* 3) internal and external interfaces from this unit +==================================================================================================*/ +#include "Psi5_Ip_Cfg_Defines.h" +#include "Mcal.h" + +/*================================================================================================== +* SOURCE FILE VERSION INFOPSI5ATION +==================================================================================================*/ +#define PSI5_IP_IRQ_VENDOR_ID 43 +#define PSI5_IP_IRQ_AR_RELEASE_MAJOR_VERSION 4 +#define PSI5_IP_IRQ_AR_RELEASE_MINOR_VERSION 7 +#define PSI5_IP_IRQ_AR_RELEASE_REVISION_VERSION 0 +#define PSI5_IP_IRQ_SW_MAJOR_VERSION 2 +#define PSI5_IP_IRQ_SW_MINOR_VERSION 0 +#define PSI5_IP_IRQ_SW_PATCH_VERSION 0 + + +/*================================================================================================== +* FILE VERSION CHECKS +==================================================================================================*/ +#ifndef DISABLE_MCAL_INTERMODULE_ASR_CHECK + /* Checks against Mcal.h */ + #if ((PSI5_IP_IRQ_AR_RELEASE_MAJOR_VERSION != MCAL_AR_RELEASE_MAJOR_VERSION) || \ + (PSI5_IP_IRQ_AR_RELEASE_MINOR_VERSION != MCAL_AR_RELEASE_MINOR_VERSION)) + #error "AUTOSAR Version Numbers of Psi5_Ip_Irq.h and Mcal.h are different" + #endif +#endif + +/* Checks against Psi5_Ip_Cfg_Defines.h */ +#if (PSI5_IP_IRQ_VENDOR_ID != PSI5_IP_CFG_DEFINES_VENDOR_ID) + #error "Psi5_Ip_Irq.h and Psi5_Ip_Cfg_Defines.h have different vendor ids" +#endif +#if ((PSI5_IP_IRQ_AR_RELEASE_MAJOR_VERSION != PSI5_IP_CFG_DEFINES_AR_RELEASE_MAJOR_VERSION) || \ + (PSI5_IP_IRQ_AR_RELEASE_MINOR_VERSION != PSI5_IP_CFG_DEFINES_AR_RELEASE_MINOR_VERSION) || \ + (PSI5_IP_IRQ_AR_RELEASE_REVISION_VERSION != PSI5_IP_CFG_DEFINES_AR_RELEASE_REVISION_VERSION) \ + ) + #error "AUTOSAR Version Numbers of Psi5_Ip_Irq.h and Psi5_Ip_Cfg_Defines.h are different" +#endif +#if ((PSI5_IP_IRQ_SW_MAJOR_VERSION != PSI5_IP_CFG_DEFINES_SW_MAJOR_VERSION) || \ + (PSI5_IP_IRQ_SW_MINOR_VERSION != PSI5_IP_CFG_DEFINES_SW_MINOR_VERSION) || \ + (PSI5_IP_IRQ_SW_PATCH_VERSION != PSI5_IP_CFG_DEFINES_SW_PATCH_VERSION) \ + ) + #error "Software Version Numbers of Psi5_Ip_Irq.h and Psi5_Ip_Cfg_Defines.h are different" +#endif + +/*================================================================================================== +* CONSTANTS +==================================================================================================*/ + +/*================================================================================================== +* DEFINES AND MACROS +==================================================================================================*/ + +/*================================================================================================== +* ENUMS +==================================================================================================*/ + +/*================================================================================================== +* STRUCTURES AND OTHER TYPEDEFS +==================================================================================================*/ + +/*================================================================================================== +* GLOBAL VARIABLE DECLARATIONS +==================================================================================================*/ + +/*================================================================================================== +* FUNCTION PROTOTYPES +==================================================================================================*/ + +#define PSI5_START_SEC_CODE +#include "Psi5_MemMap.h" + +#ifdef PSI5_IP_ENABLE_INTERRUPTS_PSI5_0_CH0 +/*FUNCTION********************************************************************** + * + * Function Name : Psi5_IRQ_Handle_PSI5_0_CH0 + * Description : Must be mapped to the generic interrupt of instace 0 channel 0. + *END**************************************************************************/ +ISR(Psi5_IRQ_Handle_PSI5_0_CH0); +#endif + +#ifdef PSI5_IP_ENABLE_INTERRUPTS_PSI5_0_CH1 +/*FUNCTION********************************************************************** + * + * Function Name : Psi5_IRQ_Handle_PSI5_0_CH0 + * Description : Must be mapped to the generic interrupt of instace 0 channel 1. + *END**************************************************************************/ +ISR(Psi5_IRQ_Handle_PSI5_0_CH1); +#endif + +#ifdef PSI5_IP_ENABLE_INTERRUPTS_PSI5_0_CH2 +/*FUNCTION********************************************************************** + * + * Function Name : Psi5_IRQ_Handle_PSI5_0_CH0 + * Description : Must be mapped to the generic interrupt of instace 0 channel 2. + *END**************************************************************************/ +ISR(Psi5_IRQ_Handle_PSI5_0_CH2); +#endif + +#ifdef PSI5_IP_ENABLE_INTERRUPTS_PSI5_0_CH3 +/*FUNCTION********************************************************************** + * + * Function Name : Psi5_IRQ_Handle_PSI5_0_CH0 + * Description : Must be mapped to the generic interrupt of instace 0 channel 3. + *END**************************************************************************/ +ISR(Psi5_IRQ_Handle_PSI5_0_CH3); +#endif + +#ifdef PSI5_IP_ENABLE_INTERRUPTS_PSI5_1_CH0 +/*FUNCTION********************************************************************** + * + * Function Name : Psi5_IRQ_Handle_PSI5_1_CH0 + * Description : Must be mapped to the generic interrupt of instace 1 channel 0. + *END**************************************************************************/ +ISR(Psi5_IRQ_Handle_PSI5_1_CH0); +#endif + +#ifdef PSI5_IP_ENABLE_INTERRUPTS_PSI5_1_CH1 +/*FUNCTION********************************************************************** + * + * Function Name : Psi5_IRQ_Handle_PSI5_1_CH0 + * Description : Must be mapped to the generic interrupt of instace 1 channel 1. + *END**************************************************************************/ +ISR(Psi5_IRQ_Handle_PSI5_1_CH1); +#endif + +#ifdef PSI5_IP_ENABLE_INTERRUPTS_PSI5_1_CH2 +/*FUNCTION********************************************************************** + * + * Function Name : Psi5_IRQ_Handle_PSI5_1_CH0 + * Description : Must be mapped to the generic interrupt of instace 1 channel 2. + *END**************************************************************************/ +ISR(Psi5_IRQ_Handle_PSI5_1_CH2); +#endif + +#ifdef PSI5_IP_ENABLE_INTERRUPTS_PSI5_1_CH3 +/*FUNCTION********************************************************************** + * + * Function Name : Psi5_IRQ_Handle_PSI5_0_CH0 + * Description : Must be mapped to the generic interrupt of instace 1 channel 3. + *END**************************************************************************/ +ISR(Psi5_IRQ_Handle_PSI5_1_CH3); +#endif + +#define PSI5_STOP_SEC_CODE +#include "Psi5_MemMap.h" + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +/*! @}*/ /* End of addtogroup psi5 */ + +#endif /* PSI5_IP_H */ diff --git a/s32/drivers/s32ze/Psi5/include/Psi5_Ip_Types.h b/s32/drivers/s32ze/Psi5/include/Psi5_Ip_Types.h new file mode 100644 index 000000000..7ac7373c8 --- /dev/null +++ b/s32/drivers/s32ze/Psi5/include/Psi5_Ip_Types.h @@ -0,0 +1,440 @@ +/* + * Copyright 2021-2024 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef PSI5_IP_TYPES_H +#define PSI5_IP_TYPES_H + +/** +* @file Psi5_Ip_Types.h +* +* @addtogroup PSI5_IP PSI5 IPV Driver +* @{ +*/ + + +#ifdef __cplusplus +extern "C"{ +#endif + +/*=============================================================================================== + INCLUDE FILES + 1) system and project includes + 2) needed interfaces from external units + 3) internal and external interfaces from this unit +===============================================================================================*/ +#include "Psi5_Ip_Cfg_Defines.h" +/*=============================================================================================== + SOURCE FILE VERSION INFORMATION +===============================================================================================*/ +#define PSI5_IP_TYPES_VENDOR_ID 43 +#define PSI5_IP_TYPES_AR_RELEASE_MAJOR_VERSION 4 +#define PSI5_IP_TYPES_AR_RELEASE_MINOR_VERSION 7 +#define PSI5_IP_TYPES_AR_RELEASE_REVISION_VERSION 0 +#define PSI5_IP_TYPES_SW_MAJOR_VERSION 2 +#define PSI5_IP_TYPES_SW_MINOR_VERSION 0 +#define PSI5_IP_TYPES_SW_PATCH_VERSION 0 + +/*================================================================================================== +* FILE VERSION CHECKS +==================================================================================================*/ +/* Checks against Psi5_Ip_Cfg_Defines.h */ +#if (PSI5_IP_TYPES_VENDOR_ID != PSI5_IP_CFG_DEFINES_VENDOR_ID) + #error "Psi5_Ip_Types.h and Psi5_Ip_Cfg_Defines.h have different vendor ids" +#endif +#if ((PSI5_IP_TYPES_AR_RELEASE_MAJOR_VERSION != PSI5_IP_CFG_DEFINES_AR_RELEASE_MAJOR_VERSION) || \ + (PSI5_IP_TYPES_AR_RELEASE_MINOR_VERSION != PSI5_IP_CFG_DEFINES_AR_RELEASE_MINOR_VERSION) || \ + (PSI5_IP_TYPES_AR_RELEASE_REVISION_VERSION != PSI5_IP_CFG_DEFINES_AR_RELEASE_REVISION_VERSION)) + #error "AUTOSAR Version Numbers of Psi5_Ip_Types.h and Psi5_Ip_Cfg_Defines.h are different" +#endif +#if ((PSI5_IP_TYPES_SW_MAJOR_VERSION != PSI5_IP_CFG_DEFINES_SW_MAJOR_VERSION) || \ + (PSI5_IP_TYPES_SW_MINOR_VERSION != PSI5_IP_CFG_DEFINES_SW_MINOR_VERSION) || \ + (PSI5_IP_TYPES_SW_PATCH_VERSION != PSI5_IP_CFG_DEFINES_SW_PATCH_VERSION)) + #error "Software Version Numbers of Psi5_Ip_Types.h and Psi5_Ip_Cfg_Defines.h are different" +#endif +/*================================================================================================== +* CONSTANTS +==================================================================================================*/ + +/*================================================================================================== +* ENUMS +==================================================================================================*/ +/*! + * @brief PSI5 Rx mode + * + * Possible values for setting the reception mode + * + * Implements : psi5_rx_mode_Class + */ +typedef enum +{ + PSI5_ASYNCHRONOUS = 0, /*!< Asynchronous mode (Rx only)*/ + PSI5_SYNCHRONOUS /*!< Synchronous mode (Rx and Tx)*/ +} Psi5_Ip_ChannelModeType; + +/*! + * @brief PSI5 Tx mode + * + * Possible values for setting the transmission mode + * + * Implements : psi5x_mode_Class + */ +typedef enum +{ + PSI5_TX_MODE_0 = 0, /*!< Short Frame(V1.3) with 31 "1s" as the start condition */ + PSI5_TX_MODE_1, /*!< Short Frame(V1.3) with 5 "0s" as the start condition */ + PSI5_TX_MODE_2, /*!< Long Frame(V1.3) with 31 "1s" as the start condition */ + PSI5_TX_MODE_3, /*!< Long Frame(V1.3) with 5 "0s" as the start condition */ + PSI5_TX_MODE_4, /*!< X-Long Frame(V1.3) with 31 "1s" as the start condition */ + PSI5_TX_MODE_5, /*!< X-Long Frame(V1.3) with 5 "0s" as the start condition */ + PSI5_TX_MODE_6, /*!< XX-Long (V2.0) */ + PSI5_TX_MODE_7 /*!< Non Standard Length */ +} Psi5_Ip_TxModeType; + +/*! + * @brief PSI5 Sync state + * + * Possible values for setting the pulse generation state + * + * Implements : psi5_sync_state_Class + */ +typedef enum +{ + PSI5_SYNC_STATE_2 = 1, /*!< Periodic Sync Pulse Generation with ECU-to-sensor Communication */ + PSI5_SYNC_STATE_1 = 3, /*!< Periodic Sync Pulse Generation (without pulse length modulation) */ + PSI5_SYNC_STATE_4 = 5, /*!< Event triggered sync pulse, including ECU-to-sensor communication */ + PSI5_SYNC_STATE_3 = 7 /*!< Event triggered (e.g. angle synchronous) sync pulses */ +} Psi5_Ip_SyncStateType; + +/*! + * @brief PSI5 instance id type + * + * Type for holding instance id + * + * Implements : Psi5_InstanceType_Class + */ +typedef enum +{ + PSI5_INSTANCE0 = 0u, /*!< Instance 0*/ + PSI5_INSTANCE1 /*!< Instance 1*/ +} Psi5_Ip_InstanceIdType; + +/*! + * @brief PSI5 DMA mode type + * + * Type for holding Dma mode + * + */ +typedef enum +{ + PSI5_DMA_MODE_CONF1 = 0u, /*!< DMA rewquest is disable*/ + PSI5_DMA_MODE_CONF2 = 1u, /*!< DMA request transfer for PSI5 message and diagnostic*/ + PSI5_DMA_MODE_CONF3 = 2u, /*!< DMA request transfer for PSI5 message only*/ + PSI5_DMA_MODE_CONF4 = 3u, /*!< DMA request transfer for PSI5 diagnostic only*/ +} Psi5_Ip_Psi5DmaModeType; + + +typedef uint8 Psi5_Ip_HwChannelIdType; + +/*================================================================================================== +* DEFINES AND MACROS +==================================================================================================*/ + +/* Get PSI5 hw Instance Id */ +#define PSI5_GET_HW_INSTANCE(internalMappingCh) (((((uint8)internalMappingCh) >> ((uint8)4u)) == 0u) ? PSI5_INSTANCE0 : PSI5_INSTANCE1) + +/* Get PSI5 hw channel Id */ +#define PSI5_GET_HW_CHANNEL(internalMappingCh) ((uint8)(((uint8)internalMappingCh) & (uint8)0x0Fu)) + +/*================================================================================================== +* STRUCTURES AND OTHER TYPEDEFS +==================================================================================================*/ + +/** + * @brief PSI5 event structure + * + * Contains data of event flags. + */ +typedef struct +{ + /* PSI5 event flags */ + boolean Psi5_Psi5MessageReceived; /*!< PSI5 Message Received Event */ + boolean Psi5_Psi5MessageOverwrite; /*!< PSI5 Message Overwrite Event */ + boolean Psi5_Psi5MessageErrorsPresent; /*!< PSI5 Message Errors Present Event */ + + /* SMC event flags */ + boolean Psi5_SmcMessageReceived; /*!< SMC Message Received Event */ + boolean Psi5_SmcMessageOverwrite; /*!< SMC Message Overwrite Event */ + boolean Psi5_SmcMessageCRCError; /*!< SMC Message CRC Error Event */ + + /* Tx event flags */ + boolean Psi5_TxDataOverwrite; /*!< Data register overwrite */ + boolean Psi5_DriverReadyToTransmit; /*!< Driver is ready to transmit new data */ + + /* PSI5 DMA event flags */ + boolean Psi5_Psi5DmaOverflow; /*!< DMA FIFO is FULL */ + boolean Psi5_Psi5DmaUnderflow; /*!< Underflow happens when the software reads the PSI5 message/error FIFO though the DPMR/DDSR, beyond the available message */ + boolean Psi5_Psi5DmaTransferComplete; /*!< DMA Transfer is complete */ + + /* SMC DMA event flags */ + boolean Psi5_SmcDmaUnderflow; /*!< This happens when the DSFR has been read without a proper DMA request being asserted. The DSFR is empty and it is read with DMA */ + boolean Psi5_SmcDmaTransferComplete; /*!< DMA Transfer is complete */ +} Psi5_Ip_EventType; + +/*! + * @brief Psi5 event type needed for callback + * + * Workaround because notification is defined in IP layer + * + * Implements : Psi5_EventType_Class +*/ +typedef Psi5_Ip_EventType Psi5_EventType; + +/*! + * @brief Callback function + * + * PSI5 callback prototype. Called from IRQ. + * + * Implements : Psi5_CallbackType_func_Class + */ +typedef void(* Psi5_Ip_CallbackType)(Psi5_EventType Event); + +/*! + * @brief PSI5 slot data type + * + * Slot configuration structure + * + * Implements : psi5_slot_config_Class + */ +typedef struct +{ + uint8 slotId; /*!< Slot id number (1-6) */ + uint16 slotLen; /*!< Slot size (in us) */ + uint16 startOffs; /*!< Slot start offset (from sync pulse, in us) */ + uint8 dataSize; /*!< Data region length */ + boolean msbFirst; /*!< Data is interpreted as MSB first */ + boolean hasSMC; /*!< Contains a Slow Message Channel in bits M0/M1 */ + boolean tsCapS0; /*!< Capture time-stamp at S0, otherwise at sync */ + boolean hasParity; /*!< Contains parity error detection, CRC otherwise */ +} Psi5_Ip_SlotConfigType; + +/*! + * @brief Raw data frame + * + * A raw PSI5/SMC frame. Contains hardware specific fields. Needs conversion. + * + * Implements : psi5_raw_frame_Class + */ +typedef uint32 Psi5_Ip_RawFrameType[2u]; + +/*! + * @brief PSI5 data frame + * + * A PSI5 frame. Contains specific fields. + * + * Implements : Psi5_Ip_Psi5FrameType_Class + */ +typedef struct +{ + uint32 DATA_REGION; /*!< Data region (28 bits) */ + uint32 TIME_STAMP; /*!< Time stamp value (24 bits) */ + uint8 CRC; /*!< CRC value Parity (3 bits, 1 bit parity in C[2] if configured) */ + uint8 C; /*!< CRC error (1 bit) */ + uint8 F; /*!< No Frame error (1 bit) */ + uint8 EM; /*!< M0/1 Error (1 bit) */ + uint8 E; /*!< Electrical error (1 bit) */ + uint8 T; /*!< Timing error (1 bit) */ + uint8 SLOT_COUNTER; /*!< Slot number (3 bits) */ +} Psi5_Ip_Psi5FrameType; + +/*! + * @brief SMC data frame + * + * A SMC frame. Contains specific fields. + * + * Implements : Psi5_SmcFrameType_Class + */ +typedef struct +{ + uint16 DATA; /*!< DATA payload */ + uint8 SLOT_NO; /*!< Slot number (3 bit)*/ + uint8 CER; /*!< CRC error (1 bit) */ + uint8 OW; /*!< Overwrite status (1 bit) */ + uint8 CRC; /*!< CRC (6 bit) */ + uint8 C; /*!< Configuration bit (1 bit) */ + uint8 ID; /*!< Message ID: If C = '0' indicates ID[7:4], if C = '1' indicates ID[3:0] */ + uint8 IDDATA; /*!< Message ID/DATA: If C = '0' indicates ID[3:0], if C = '1' indicates DATA[15:12] */ +} Psi5_Ip_SmcFrameType; + +typedef Psi5_Ip_RawFrameType Psi5_RawFrameType; + +/*! + * @brief Channel rx Psi5 Dmaconfiguration structure + * + * Contains configuration data for one channel. + * + */ +typedef struct +{ + Psi5_Ip_Psi5DmaModeType psi5DmaMode; /*!< Mode of PSI5 DMA Frame*/ + const uint32 psi5DmaWatermarkDmaTrigger; /*!< Interrupt request enabled when any new message (fault-free/with fault) is received in the RAM buffer Register 'x' location [x: 0 to 31] */ + Psi5_Ip_Psi5FrameType *psi5DmaUserBuffer; /*!< DMA user data buffer for PSI5 messages */ + uint32 *psi5DmaUserDiagnosticBuffer; /*!< DMA user diagnostic buffer for PSI5 messages */ + Psi5_Ip_RawFrameType *psi5DmaInternalBuffer; /*!< DMA raw internal buffer for PSI5 messages */ + const uint8 psi5DmaChannel; /*!< Assigned DMA channel for PSI5 frames */ +} Psi5_Ip_ChannelRxPsi5DmaConfigType; + +/*! + * @brief Channel rx Smc Dmaconfiguration structure + * + * Contains configuration data for one channel. + * + */ +typedef struct +{ + Psi5_Ip_SmcFrameType *smcDmaUserBuffer; /*!< DMA user data buffer for Smc messages */ + Psi5_Ip_RawFrameType *smcDmaInternalBuffer; /*!< DMA raw internal buffer for PSI5 messages */ + const uint8 smcDmaChannel; /*!< Assigned DMA channel for SMC frames */ +} Psi5_Ip_ChannelRxSmcDmaConfigType; + +/*! + * @brief Channel rx configuration structure + * + * Contains configuration data for one channel. + * + * Implements : psi5_channel_rx_config_Class + */ +typedef struct +{ + const uint8 rxBufSize; /*!< Size of RX buffer for PSI5 messages (1 - 32) */ + const uint32 watermarkInterruptLevel; /*!< Interrupt request enabled when any new message (fault-free/with fault) is received in the RAM buffer Register 'x' location [x: 0 to 31] */ + const uint8 bitRate; /*!< 0 - 125 Kbit/s bit rate, 1 - 189 Kbit/s bit rate*/ + const Psi5_Ip_ChannelRxPsi5DmaConfigType *psi5DmaConfig; /*!< DMA buffer for PSI5 messages */ + const Psi5_Ip_ChannelRxSmcDmaConfigType *smcDmaConfig; /*!< DMA buffer for SMC messages */ + const Psi5_Ip_SlotConfigType *slotConfig; /*!< Pointer to a slot configuration list */ + const uint8 numOfSlotConfigs; /*!< Number of configurations in the slot configuration list */ +} Psi5_Ip_ChannelRxConfigType; + +/*! + * @brief Channel tx configuration structure + * + * Contains configuration data for one channel. + * + * Implements : psi5_channel_tx_config_Class + */ +typedef struct +{ + const boolean syncGlobal; /*!< Sync generator controlled by the instance */ + const boolean asyncReset; /*!< GTM reset is treated asynchronous */ + const uint16 initialPulse; /*!< Initial reset reload value for the integrated pulse generator */ + const uint16 targetPulse; /*!< Subsequent reload values for the integrated pulse generator */ + const uint8 decoderOffset; /*!< Time in us for which the manchester decoder is disabled after the falling edge of a sync pulse */ + const uint8 pulse0Width; /*!< Width (in us) for a "0" output pulse */ + const uint8 pulse1Width; /*!< Width (in us) for a "1" output pulse */ + const Psi5_Ip_TxModeType txMode; /*!< Transmitter mode, please refer to RM */ + const Psi5_Ip_SyncStateType syncState; /*!< Pulse generator state, please refer to RM */ + const uint8 txSize; /*!< Tx data length (only for TX_MODE_7) */ + const boolean txDefault1; /*!< All bits in Tx registers will default to "1" */ +} Psi5_Ip_ChannelTxConfigType; + +typedef struct +{ + const boolean errorSelect0; + const boolean errorSelect1; + const boolean errorSelect2; + const boolean errorSelect3; + const boolean errorSelect4; +} Psi5_Ip_ErrorSelectConfigType; + + +/*! + * @brief Channel configuration structure + * + * Contains configuration data for one channel. + * + * Implements : psi5_channel_config_Class + */ +typedef struct +{ + const uint8 channelId; /*!< Channel id number (0-3) */ + const Psi5_Ip_ChannelModeType channelMode; /*!< Communication mode */ + const boolean debugEnable; /*!< Enable/Disable debug mode */ + const boolean debugFreeze; /*!< Enable/Disable debug freeze */ + const Psi5_Ip_CallbackType callback; /*!< Callback data */ + const Psi5_Ip_ChannelRxConfigType *rxConfig; /*!< Rx Configuration */ + const Psi5_Ip_ChannelTxConfigType *txConfig; /*!< Tx Configuration */ + const Psi5_Ip_ErrorSelectConfigType *errorSelectConfig; /*!< Error Select Configuration */ +} Psi5_Ip_ChannelConfigType; + +/*! + * @brief Instance configuration structure + * + * PSI5 instance configuration structure. Contains all data required to configure the instance. + * + * Implements : psi5_driver_user_config_Class + */ +typedef struct +{ + const Psi5_Ip_InstanceIdType instanceId; /*!< PSI5 instance id */ + const boolean globalCtcEn; /*!< Pulse generation automatically starts at init (outcome depends on channel configuration) */ + const Psi5_Ip_ChannelConfigType *channelConfig; /*!< Pointer to a channel configuration list */ + const uint8 numOfChannels; /*!< Number of channels configured */ + const uint8 *chHwIdToIndexArrayConfig; /*!< Array with mapping of channel hw id to the index in channel config array */ +} Psi5_Ip_InstanceType; +/*! + * @brief Channels configuration structure + * + * PSI5 instance configuration structure. Contains all data required to configure the channels of an instance. + * + * Implements : psi5_driver_user_config_Class + */ +typedef struct +{ + const Psi5_Ip_InstanceType *instancesConfig; /*!< Pointer to instances configuration list */ + const uint8 numOfInstances; /*!< Number of instances configured */ + const uint8 *logicalChToHwCh; /*!< Pointer to array mapping logical channel to hardware channel */ +} Psi5_Ip_ConfigType; + +/*! + * @brief Two arrays for both types of psi5 message format (psi5 and smc) + * + * Both arrays are used in FILO mode. Contains position of received messages. + * Last value from array different than 0 correspond with position of last received message. + * + * Implements : psi5_channel_config_Class + */ +typedef struct +{ + uint8 psi5CurrentIndex; /*!< Index of last position filled in messages array */ + uint8 psi5PosMsgAvailable[PSI5_CHANNEL_CH_PMR_COUNT]; /*!< Buffer with locations of PSI5 messages available for reading. 0xFF - default, no message aavailable. Value != 0 means Position in reg NDSR. (internal use) */ + uint8 smcCurrentIndex; /*!< Index of last position filled in array */ + uint8 smcPosMsgAvailable[PSI5_CHANNEL_CH_SFR_COUNT]; /*!< Buffer with locations of SMC messages available for reading. 0xFF - default, no message aavailable. Value != 0 means Position in reg (GISR & IS_NVSM_MASK). (internal use) */ +} Psi5_Ip_AvailableMessagesType; + +/*================================================================================================== +* GLOBAL VARIABLE DECLARATIONS +==================================================================================================*/ + +/*=============================================================================================== + GLOBAL VARIABLE DECLARATIONS +===============================================================================================*/ + +/*=============================================================================================== +* FUNCTION PROTOTYPES +===============================================================================================*/ + +/*================================================================================================== +* FUNCTION PROTOTYPES +==================================================================================================*/ + + +#ifdef __cplusplus +} +#endif + +/** @} */ + +#endif /* PSI5_IP_TYPES_H */ + diff --git a/s32/drivers/s32ze/Psi5/src/Psi5_Ip.c b/s32/drivers/s32ze/Psi5/src/Psi5_Ip.c new file mode 100644 index 000000000..6abc2e67b --- /dev/null +++ b/s32/drivers/s32ze/Psi5/src/Psi5_Ip.c @@ -0,0 +1,1825 @@ +/* + * Copyright 2021-2024 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/** +* @file Psi5_Ip.c +* +* @addtogroup PSI5_IP PSI5 IPV Driver +* @{ +*/ + + +#ifdef __cplusplus +extern "C"{ +#endif + +/*================================================================================================== +* INCLUDE FILES +* 1) system and project includes +* 2) needed interfaces from external units +* 3) internal and external interfaces from this unit +==================================================================================================*/ + +#include "Mcal.h" +#include "Psi5_Ip.h" +#include "Psi5_Ip_Cfg.h" +#include "SchM_Psi5.h" + +#if (STD_ON == PSI5_IP_DMA_IS_USED) +#include "CDD_Mcl.h" +#endif + +#ifdef PSI5_IP_DEV_ERROR_DETECT +#if (STD_ON == PSI5_IP_DEV_ERROR_DETECT) + #include "Devassert.h" +#endif +#endif + +/*================================================================================================== +* SOURCE FILE VERSION INFORMATION +==================================================================================================*/ +#define PSI5_IP_VENDOR_ID_C 43 +#define PSI5_IP_AR_RELEASE_MAJOR_VERSION_C 4 +#define PSI5_IP_AR_RELEASE_MINOR_VERSION_C 7 +#define PSI5_IP_AR_RELEASE_REVISION_VERSION_C 0 +#define PSI5_IP_SW_MAJOR_VERSION_C 2 +#define PSI5_IP_SW_MINOR_VERSION_C 0 +#define PSI5_IP_SW_PATCH_VERSION_C 0 + +/*================================================================================================== +* FILE VERSION CHECKS +==================================================================================================*/ +#ifndef DISABLE_MCAL_INTERMODULE_ASR_CHECK + /* Checks against Mcal.h */ + #if ((PSI5_IP_AR_RELEASE_MAJOR_VERSION_C != MCAL_AR_RELEASE_MAJOR_VERSION) || \ + (PSI5_IP_AR_RELEASE_MINOR_VERSION_C != MCAL_AR_RELEASE_MINOR_VERSION) \ + ) + #error "AUTOSAR Version Numbers of Psi5_Ip.c and Mcal.h are different" + #endif +#endif + +/* Checks against Psi5_Ip.h */ +#if (PSI5_IP_VENDOR_ID_C != PSI5_IP_VENDOR_ID) + #error "Psi5_Ip.c and Psi5_Ip.h have different vendor ids" +#endif +#if ((PSI5_IP_AR_RELEASE_MAJOR_VERSION_C != PSI5_IP_AR_RELEASE_MAJOR_VERSION) || \ + (PSI5_IP_AR_RELEASE_MINOR_VERSION_C != PSI5_IP_AR_RELEASE_MINOR_VERSION) || \ + (PSI5_IP_AR_RELEASE_REVISION_VERSION_C != PSI5_IP_AR_RELEASE_REVISION_VERSION) \ + ) + #error "AUTOSAR Version Numbers of Psi5_Ip.c and Psi5_Ip.h are different" +#endif +#if ((PSI5_IP_SW_MAJOR_VERSION_C != PSI5_IP_SW_MAJOR_VERSION) || \ + (PSI5_IP_SW_MINOR_VERSION_C != PSI5_IP_SW_MINOR_VERSION) || \ + (PSI5_IP_SW_PATCH_VERSION_C != PSI5_IP_SW_PATCH_VERSION) \ + ) + #error "Software Version Numbers of Psi5_Ip.c and Psi5_Ip.h are different" +#endif + +/* Checks against Psi5_Ip_Cfg.h */ +#if (PSI5_IP_VENDOR_ID_C != PSI5_IP_CFG_VENDOR_ID) + #error "Psi5_Ip.c and Psi5_Ip_Cfg.h have different vendor ids" +#endif +#if ((PSI5_IP_AR_RELEASE_MAJOR_VERSION_C != PSI5_IP_CFG_AR_RELEASE_MAJOR_VERSION) || \ + (PSI5_IP_AR_RELEASE_MINOR_VERSION_C != PSI5_IP_CFG_AR_RELEASE_MINOR_VERSION) || \ + (PSI5_IP_AR_RELEASE_REVISION_VERSION_C != PSI5_IP_CFG_AR_RELEASE_REVISION_VERSION) \ + ) + #error "AUTOSAR Version Numbers of Psi5_Ip.c and Psi5_Ip_Cfg.h are different" +#endif +#if ((PSI5_IP_SW_MAJOR_VERSION_C != PSI5_IP_CFG_SW_MAJOR_VERSION) || \ + (PSI5_IP_SW_MINOR_VERSION_C != PSI5_IP_CFG_SW_MINOR_VERSION) || \ + (PSI5_IP_SW_PATCH_VERSION_C != PSI5_IP_CFG_SW_PATCH_VERSION) \ + ) + #error "Software Version Numbers of Psi5_Ip.c and Psi5_Ip_Cfg.h are different" +#endif + +#ifndef DISABLE_MCAL_INTERMODULE_ASR_CHECK + #ifdef AXBS_IP_DEV_ERROR_DETECT + #if (STD_ON == AXBS_IP_DEV_ERROR_DETECT) + /* Check if the files Psi5_Ip.c and Devassert.h are of the same version */ + #if ((PSI5_IP_AR_RELEASE_MAJOR_VERSION_C != DEVASSERT_AR_RELEASE_MAJOR_VERSION) || \ + (PSI5_IP_AR_RELEASE_MINOR_VERSION_C != DEVASSERT_AR_RELEASE_MINOR_VERSION) \ + ) + #error "AUTOSAR Version Numbers of Psi5_Ip.c and Devassert.h are different" + #endif + #endif + #endif +#endif +/*================================================================================================== +* LOCAL MACROS +==================================================================================================*/ + +/*================================================================================================== +* LOCAL TYPEDEFS (STRUCTURES, UNIONS, ENUMS) +==================================================================================================*/ + +/*================================================================================================== +* LOCAL CONSTANTS +==================================================================================================*/ + +/*================================================================================================== +* LOCAL VARIABLES +==================================================================================================*/ + +/*================================================================================================== +* GLOBAL CONSTANTS +==================================================================================================*/ + +/*! + *Instance base addresses + */ +static const PSI5_MemMapPtr Psi5_Ip_axBaseAddresses[PSI5_INSTANCE_COUNT] = IP_PSI5_BASE_PTRS; + +/*================================================================================================== +* GLOBAL VARIABLES +==================================================================================================*/ +#if (STD_ON == PSI5_IP_MULTIPARTITION_SUPPORT) +#define PSI5_START_SEC_VAR_SHARED_CLEARED_UNSPECIFIED_NO_CACHEABLE +#include "Psi5_MemMap.h" + +VAR_SEC_NOCACHE(Psi5_Ip_pUsedConfig) static Psi5_Ip_ConfigType const *Psi5_Ip_pUsedConfig = NULL_PTR; +VAR_SEC_NOCACHE(Psi5_Ip_axMessages) static Psi5_Ip_AvailableMessagesType Psi5_Ip_axMessages[PSI5_INSTANCE_COUNT][PSI5_CHANNEL_COUNT]; +VAR_SEC_NOCACHE(Psi5_Ip_bDriverInitialized) static boolean Psi5_Ip_bDriverInitialized = FALSE; + +#define PSI5_STOP_SEC_VAR_SHARED_CLEARED_UNSPECIFIED_NO_CACHEABLE +#include "Psi5_MemMap.h" +#else +#define PSI5_START_SEC_CONFIG_DATA_UNSPECIFIED +#include "Psi5_MemMap.h" + +static Psi5_Ip_ConfigType const *Psi5_Ip_pUsedConfig = NULL_PTR; + +#define PSI5_STOP_SEC_CONFIG_DATA_UNSPECIFIED +#include "Psi5_MemMap.h" + +#define PSI5_START_SEC_VAR_CLEARED_UNSPECIFIED +#include "Psi5_MemMap.h" + +static Psi5_Ip_AvailableMessagesType Psi5_Ip_axMessages[PSI5_INSTANCE_COUNT][PSI5_CHANNEL_COUNT]; + +static boolean Psi5_Ip_bDriverInitialized = FALSE; + +#define PSI5_STOP_SEC_VAR_CLEARED_UNSPECIFIED +#include "Psi5_MemMap.h" +#endif + +/*================================================================================================== +* LOCAL FUNCTION PROTOTYPES +==================================================================================================*/ + +#define PSI5_START_SEC_CODE +#include "Psi5_MemMap.h" +#if (STD_ON == PSI5_IP_GET_PSI5_FRAME_API) +static Std_ReturnType Psi5_Hw_GetRawPsi5Frame(const Psi5_Ip_InstanceIdType instance, + const Psi5_Ip_HwChannelIdType Psi5ChannelId, + Psi5_Ip_RawFrameType *raw + ); +#endif + +#if ((STD_ON == PSI5_IP_GET_PSI5_FRAME_API) || (STD_ON == PSI5_IP_DMA_PSI5_FRAME_IS_USED)) +static void Psi5_Hw_ConvertRawPsi5Frame(Psi5_Ip_Psi5FrameType *frame, + Psi5_Ip_RawFrameType *raw, + const Psi5_Ip_SlotConfigType *states + ); +#endif +#if (STD_ON == PSI5_IP_GET_SMC_FRAME_API) +static Std_ReturnType Psi5_Hw_GetRawSmcFrame(const Psi5_Ip_InstanceIdType instance, + const Psi5_Ip_HwChannelIdType Psi5ChannelId, + Psi5_Ip_RawFrameType *raw + ); +#endif +#if ((STD_ON == PSI5_IP_GET_SMC_FRAME_API) || (STD_ON == PSI5_IP_DMA_SMC_FRAME_IS_USED)) +static void Psi5_Hw_ConvertRawSmcFrame(Psi5_Ip_SmcFrameType *frame, + Psi5_Ip_RawFrameType *raw + ); +#endif +static void Psi5_Hw_ConfigureSlot(const Psi5_Ip_InstanceIdType instance, + const Psi5_Ip_HwChannelIdType Psi5ChannelId, + const Psi5_Ip_SlotConfigType *slot + ); +static void Psi5_Hw_EnterConfigMode(const Psi5_Ip_InstanceIdType instance, + const Psi5_Ip_HwChannelIdType Psi5ChannelId + ); +static void Psi5_Hw_EnterNormalMode(const Psi5_Ip_InstanceIdType instanceId, + const Psi5_Ip_HwChannelIdType Psi5ChannelId + ); +static void Psi5_Hw_ConfigureTx(const Psi5_Ip_InstanceIdType instanceId, + const Psi5_Ip_ChannelConfigType *chCfg + ); +static void Psi5_Hw_ConfigureRx(const Psi5_Ip_InstanceIdType instanceId, + const Psi5_Ip_ChannelConfigType *chCfg + ); +static void Psi5_Hw_ConfigurePulseGenerator(const Psi5_Ip_InstanceIdType instanceId, + const Psi5_Ip_ChannelConfigType *chCfg + ); +#if (STD_ON == PSI5_IP_DMA_IS_USED) +static void Psi5_Hw_ConfigureDma(const Psi5_Ip_InstanceIdType instanceId, + const Psi5_Ip_ChannelConfigType *chCfg + ); +#endif +static void Psi5_Hw_InstanceDisable(const Psi5_Ip_InstanceIdType instanceId, + const boolean state + ); +static Std_ReturnType Psi5_Hw_StartGlobalCtc(const Psi5_Ip_InstanceIdType instanceId, + const boolean state + ); +static void Psi5_Hw_ResetRegisters(const Psi5_Ip_InstanceIdType instance); +#if ((STD_ON == PSI5_IP_GET_TRANSMISSION_STATUS_API) || (STD_ON == PSI5_IP_TRANSMIT_API)) +static boolean Psi5_Hw_IsDataRegisterReady(const Psi5_Ip_InstanceIdType instance, + const Psi5_Ip_HwChannelIdType Psi5ChannelId + ); +#endif +static void Psi5_EnterConfigMode(const Psi5_Ip_InstanceType *instance); +static void Psi5_EnterNormalMode(const Psi5_Ip_InstanceType *instance); +static void Psi5_ConfigureSlots(const Psi5_Ip_InstanceIdType instanceId, + const Psi5_Ip_ChannelConfigType *channelConfig + ); +static void Psi5_ConfigureChannel(const Psi5_Ip_InstanceIdType instanceId, + const Psi5_Ip_ChannelConfigType * chCfg + ); +static void Psi5_ConfigureChannels(const Psi5_Ip_InstanceType * instance); + +static void Psi5_Hw_GetTxEvents(const Psi5_Ip_InstanceIdType instance, + const Psi5_Ip_HwChannelIdType Psi5ChannelId, + Psi5_Ip_EventType *const Events + ); +static void Psi5_Hw_GetSmcEvents(const Psi5_Ip_InstanceIdType instance, + const Psi5_Ip_HwChannelIdType Psi5ChannelId, + Psi5_Ip_EventType *const Events + ); +static void Psi5_Hw_GetPsi5Events(const Psi5_Ip_InstanceIdType instance, + const Psi5_Ip_HwChannelIdType Psi5ChannelId, + Psi5_Ip_EventType *const Events + ); +static void Psi5_Hw_GetEvents(const Psi5_Ip_InstanceIdType Psi5InstanceId, + const Psi5_Ip_HwChannelIdType Psi5ChannelId, + Psi5_Ip_EventType *const Events + ); +static void Psi5_Hw_EnableInterrupts(const Psi5_Ip_InstanceIdType instance, + const Psi5_Ip_ChannelConfigType *chCfg, + const boolean Enable + ); +static void Psi5_Hw_ClearEvents(const Psi5_Ip_InstanceIdType Psi5InstanceId, + const Psi5_Ip_HwChannelIdType Psi5ChannelId + ); + +/** + * + * Function Name : Psi5_Hw_GetTxEvents + * Description : Returns active Tx events + * + *END**************************************************************************/ +static void Psi5_Hw_GetTxEvents(const Psi5_Ip_InstanceIdType instance, + const Psi5_Ip_HwChannelIdType Psi5ChannelId, + Psi5_Ip_EventType *const Events + ) +{ + const PSI5_MemMapPtr base = Psi5_Ip_axBaseAddresses[instance]; + const uint8 arrayIndex = Psi5_Ip_pUsedConfig->instancesConfig[instance].chHwIdToIndexArrayConfig[Psi5ChannelId]; + const Psi5_Ip_ChannelConfigType *config = &(Psi5_Ip_pUsedConfig->instancesConfig[instance].channelConfig[arrayIndex]); + uint32 regValue; + + if (NULL_PTR != config->txConfig) + { + uint32 txMaskOvr = (config->txConfig->txMode == PSI5_TX_MODE_7) ? PSI5_CH_GISR_IS_DSROW_MASK : PSI5_CH_GISR_IS_PROW_MASK; + uint32 txMaskOvrSet = (config->txConfig->txMode == PSI5_TX_MODE_7) ? PSI5_CH_GICR_IE_DSROW_MASK : PSI5_CH_GICR_IE_PROW_MASK; + uint32 txMaskRdy = (config->txConfig->txMode == PSI5_TX_MODE_7) ? PSI5_CH_GISR_DSR_RDY_MASK : PSI5_CH_GISR_DPR_RDY_MASK; + uint32 txMaskRdySet = (config->txConfig->txMode == PSI5_TX_MODE_7) ? PSI5_CH_GICR_IE_DSRR_MASK : PSI5_CH_GICR_IE_PRR_MASK; + + regValue = base->CHANNEL[Psi5ChannelId].CH_GISR & txMaskOvr; + + /* Data prep overwrite */ + if (0u != regValue) + { + if (0u != (base->CHANNEL[Psi5ChannelId].CH_GICR & txMaskOvrSet)) + { + Events->Psi5_TxDataOverwrite = TRUE; + + /*Disable interrupt, it will be re-enabled in the transmit function*/ + base->CHANNEL[Psi5ChannelId].CH_GICR &= ~txMaskOvrSet; + } + /*clear interrupt*/ + base->CHANNEL[Psi5ChannelId].CH_GISR |= txMaskOvr; + } + + regValue = base->CHANNEL[Psi5ChannelId].CH_GISR & txMaskRdy; + /* Data prep ready */ + if (0u != regValue) + { + if (0u != (base->CHANNEL[Psi5ChannelId].CH_GICR & txMaskRdySet)) + { + Events->Psi5_DriverReadyToTransmit = TRUE; + + /*Disable interrupt, it will be re-enabled in the transmit function*/ + base->CHANNEL[Psi5ChannelId].CH_GICR &= ~txMaskRdySet; + } + /*There is no interrupt flag, does not need clear interrupt*/ + } + } +} + +/** + * + * Function Name : Psi5_Hw_GetSmcEvents + * Description : Returns active SMC events + * + *END**************************************************************************/ +static void Psi5_Hw_GetSmcEvents(const Psi5_Ip_InstanceIdType instance, + const Psi5_Ip_HwChannelIdType Psi5ChannelId, + Psi5_Ip_EventType *const Events + ) +{ + const PSI5_MemMapPtr base = Psi5_Ip_axBaseAddresses[instance]; +#if (STD_ON == PSI5_IP_DMA_SMC_FRAME_IS_USED) + const uint8 arrayIndex = Psi5_Ip_pUsedConfig->instancesConfig[instance].chHwIdToIndexArrayConfig[Psi5ChannelId]; + const Psi5_Ip_ChannelConfigType *config = &(Psi5_Ip_pUsedConfig->instancesConfig[instance].channelConfig[arrayIndex]); +#endif + + uint8 tempPosition = 0u; + uint8 regRavlue; + +#if (STD_ON == PSI5_IP_DMA_SMC_FRAME_IS_USED) + /* SMC DMA / Normal */ + if (NULL_PTR != config->rxConfig->smcDmaConfig) + { + /* Ready */ + if (0u != (base->CHANNEL[Psi5ChannelId].CH_DSR & PSI5_CH_DSR_IS_DMA_TF_SF_MASK)) + { + if (0u != (base->CHANNEL[Psi5ChannelId].CH_DCR & PSI5_CH_DCR_IE_DMA_TF_SF_MASK)) + { + Events->Psi5_SmcDmaTransferComplete = TRUE; + + /*Convert data*/ + Psi5_Hw_ConvertRawSmcFrame(config->rxConfig->smcDmaConfig->smcDmaUserBuffer, config->rxConfig->smcDmaConfig->smcDmaInternalBuffer); + } + + /*clear interrupt flag*/ + base->CHANNEL[Psi5ChannelId].CH_DSR |= PSI5_CH_DSR_IS_DMA_TF_SF_MASK; + } + + /* Underflow */ + if (0u != (base->CHANNEL[Psi5ChannelId].CH_DSR & PSI5_CH_DSR_IS_DMA_SFUF_MASK)) + { + if (0u != (base->CHANNEL[Psi5ChannelId].CH_DCR & PSI5_CH_DCR_IE_DMA_SFUF_MASK)) + { + Events->Psi5_SmcDmaUnderflow = TRUE; + } + + /*clear interrupt flag*/ + base->CHANNEL[Psi5ChannelId].CH_DSR |= PSI5_CH_DSR_IS_DMA_SFUF_MASK; + } + } + else +#endif + { + /* SMC Rx Complete */ + if (0u != (base->CHANNEL[Psi5ChannelId].CH_GISR & PSI5_CH_GISR_IS_NVSM_MASK)) + { + /* Mark event */ + Events->Psi5_SmcMessageReceived = TRUE; + + regRavlue = (uint8)((base->CHANNEL[Psi5ChannelId].CH_GISR & PSI5_CH_GISR_IS_NVSM_MASK) >> PSI5_CH_GISR_IS_NVSM_SHIFT); + + /* Iterate through bits of regRavlue till we find a set bit */ + while ((((regRavlue >> tempPosition) & 1u) == 0u) && (tempPosition < (PSI5_CHANNEL_CH_SFR_COUNT - 1u))) + { + /* increment position */ + tempPosition++; + } + + if (0XFFu == Psi5_Ip_axMessages[instance][Psi5ChannelId].smcCurrentIndex) + { + Psi5_Ip_axMessages[instance][Psi5ChannelId].smcCurrentIndex = 0u; + } + + /*increment index of array and save bit position*/ + Psi5_Ip_axMessages[instance][Psi5ChannelId].smcPosMsgAvailable[Psi5_Ip_axMessages[instance][Psi5ChannelId].smcCurrentIndex] = tempPosition; + + if ((Psi5_Ip_axMessages[instance][Psi5ChannelId].smcCurrentIndex + 1u) >= PSI5_CHANNEL_CH_SFR_COUNT) + { + Psi5_Ip_axMessages[instance][Psi5ChannelId].smcCurrentIndex = 0u; + } + else + { + Psi5_Ip_axMessages[instance][Psi5ChannelId].smcCurrentIndex++; + } + + /*clear interrupt flag*/ + base->CHANNEL[Psi5ChannelId].CH_GISR |= (uint32)((uint32)1u << (uint32)tempPosition); + } + + /* SMC Overwrite */ + if (0u != (base->CHANNEL[Psi5ChannelId].CH_GISR & PSI5_CH_GISR_IS_OWSM_MASK)) + { + Events->Psi5_SmcMessageOverwrite = TRUE; + + regRavlue = (uint8)((base->CHANNEL[Psi5ChannelId].CH_GISR & PSI5_CH_GISR_IS_OWSM_MASK) >> PSI5_CH_GISR_IS_OWSM_SHIFT); + + /* Iterate through bits of regRavlue till we find a set bit */ + while ((((regRavlue >> tempPosition) & 1u) == 0u) && (tempPosition < (PSI5_CHANNEL_CH_SFR_COUNT - 1u))) + { + /* increment position */ + tempPosition++; + } + + /*clear interrupt flag*/ + base->CHANNEL[Psi5ChannelId].CH_GISR |= (uint32)((uint32)1u << (uint32)tempPosition); + } + + /* SMC error */ + if (0u != (base->CHANNEL[Psi5ChannelId].CH_GISR & PSI5_CH_GISR_IS_CESM_MASK)) + { + Events->Psi5_SmcMessageCRCError = TRUE; + + regRavlue = (uint8)((base->CHANNEL[Psi5ChannelId].CH_GISR & PSI5_CH_GISR_IS_CESM_MASK) >> PSI5_CH_GISR_IS_CESM_SHIFT); + + /* Iterate through bits of regRavlue till we find a set bit */ + while ((((regRavlue >> tempPosition) & 1u) == 0u) && (tempPosition < (PSI5_CHANNEL_CH_SFR_COUNT - 1u))) + { + /* increment position */ + tempPosition++; + } + + /*clear interrupt flag*/ + base->CHANNEL[Psi5ChannelId].CH_GISR |= (uint32)((uint32)1u << (uint32)tempPosition); + } + } +} + +/** + * + * Function Name : Psi5_Hw_GetPsi5Events + * Description : Returns active PSI5 events + * + *END**************************************************************************/ +static void Psi5_Hw_GetPsi5Events(const Psi5_Ip_InstanceIdType instance, + const Psi5_Ip_HwChannelIdType Psi5ChannelId, + Psi5_Ip_EventType *const Events + ) +{ + PSI5_MemMapPtr base = Psi5_Ip_axBaseAddresses[instance]; +#if (STD_ON == PSI5_IP_DMA_PSI5_FRAME_IS_USED) + const uint8 arrayIndex = Psi5_Ip_pUsedConfig->instancesConfig[instance].chHwIdToIndexArrayConfig[Psi5ChannelId]; + const Psi5_Ip_ChannelConfigType * config = &(Psi5_Ip_pUsedConfig->instancesConfig[instance].channelConfig[arrayIndex]); + const Psi5_Ip_SlotConfigType * slotStates; + const Psi5_Ip_ChannelRxPsi5DmaConfigType * psi5DmaConfig; + uint8 index = 0; +#endif + + uint32 regRavlue; + uint8 tempPosition = 0u; + +#if (STD_ON == PSI5_IP_DMA_PSI5_FRAME_IS_USED) + /* PSI5 DMA */ + if (NULL_PTR != config->rxConfig->psi5DmaConfig) + { + /* Ready */ + if ((0U != (base->CHANNEL[Psi5ChannelId].CH_DSR & PSI5_CH_DSR_IS_DMA_TF_PM_DS_MASK)) && (0U != (base->CHANNEL[Psi5ChannelId].CH_DCR & PSI5_CH_DCR_IE_DMA_TF_PM_DS_MASK))) + { + Events->Psi5_Psi5DmaTransferComplete = TRUE; + + /*clear interrupt flag*/ + base->CHANNEL[Psi5ChannelId].CH_DSR |= PSI5_CH_DSR_IS_DMA_TF_PM_DS_MASK; + + psi5DmaConfig = config->rxConfig->psi5DmaConfig; + /*Convert data if Mode is PSI5_DMA_MODE_CONF2 or PSI5_DMA_MODE_CONF3*/ + if(PSI5_DMA_MODE_CONF4 != psi5DmaConfig->psi5DmaMode) + { + slotStates = config->rxConfig->slotConfig; + + for(index = 0U;index< psi5DmaConfig->psi5DmaWatermarkDmaTrigger; index++) + { + Psi5_Hw_ConvertRawPsi5Frame(&(psi5DmaConfig->psi5DmaUserBuffer[index]), &(psi5DmaConfig->psi5DmaInternalBuffer[index]), slotStates); + } + } + /*store diagnostic bits if Mode is PSI5_DMA_MODE_CONF2*/ + if(PSI5_DMA_MODE_CONF2 == psi5DmaConfig->psi5DmaMode) + { + psi5DmaConfig->psi5DmaUserDiagnosticBuffer[0U] = psi5DmaConfig->psi5DmaInternalBuffer[psi5DmaConfig->psi5DmaWatermarkDmaTrigger][0U]; + psi5DmaConfig->psi5DmaUserDiagnosticBuffer[1U] = psi5DmaConfig->psi5DmaInternalBuffer[psi5DmaConfig->psi5DmaWatermarkDmaTrigger][1U]; + } + /*store diagnostic bits if Mode is PSI5_DMA_MODE_CONF4*/ + if(PSI5_DMA_MODE_CONF4 == psi5DmaConfig->psi5DmaMode) + { + psi5DmaConfig->psi5DmaUserDiagnosticBuffer[0U] = psi5DmaConfig->psi5DmaInternalBuffer[0U][0U]; + psi5DmaConfig->psi5DmaUserDiagnosticBuffer[1U] = psi5DmaConfig->psi5DmaInternalBuffer[0U][1U]; + } + } + + /* Underflow */ + if ((0u != (base->CHANNEL[Psi5ChannelId].CH_DSR & PSI5_CH_DSR_IS_DMA_PM_DS_UF_MASK)) && (0u != (base->CHANNEL[Psi5ChannelId].CH_DCR & PSI5_CH_DCR_IE_DMA_TF_PM_DS_MASK))) + { + Events->Psi5_Psi5DmaUnderflow = TRUE; + + /*clear interrupt flag*/ + base->CHANNEL[Psi5ChannelId].CH_DSR |= PSI5_CH_DSR_IS_DMA_PM_DS_UF_MASK; + } + + /* Overflow */ + if ((0u != (base->CHANNEL[Psi5ChannelId].CH_DSR & PSI5_CH_DSR_IS_DMA_PM_DS_FIFO_FULL_MASK)) && (0u != (base->CHANNEL[Psi5ChannelId].CH_DCR & PSI5_CH_DCR_IE_DMA_PM_DS_FIFO_FULL_MASK))) + { + Events->Psi5_Psi5DmaOverflow = TRUE; + + /*clear interrupt flag*/ + base->CHANNEL[Psi5ChannelId].CH_DSR |= PSI5_CH_DSR_IS_DMA_PM_DS_FIFO_FULL_MASK; + } + } + else +#endif + { + /* PSI5 Rx Complete */ + if ((0u != base->CHANNEL[Psi5ChannelId].CH_NDSR) && (0u != (base->CHANNEL[Psi5ChannelId].CH_NDICR & PSI5_CH_NDICR_IE_ND_MASK))) + { + /* Mark event */ + Events->Psi5_Psi5MessageReceived = TRUE; + + regRavlue = base->CHANNEL[Psi5ChannelId].CH_NDSR; + + /* Iterate through bits of regRavlue till we find a set bit */ + while ((((regRavlue >> tempPosition) & 1u) == 0u) && (tempPosition < (PSI5_CHANNEL_CH_PMR_COUNT - 1u))) + { + /* increment position */ + tempPosition++; + } + + /*0xFF means that there are no messages waiting to be read*/ + if (0xFFu == Psi5_Ip_axMessages[instance][Psi5ChannelId].psi5CurrentIndex) + { + Psi5_Ip_axMessages[instance][Psi5ChannelId].psi5CurrentIndex = 0u; + } + + /*save bit position*/ + Psi5_Ip_axMessages[instance][Psi5ChannelId].psi5PosMsgAvailable[Psi5_Ip_axMessages[instance][Psi5ChannelId].psi5CurrentIndex] = tempPosition; + + if ((Psi5_Ip_axMessages[instance][Psi5ChannelId].psi5CurrentIndex + 1u) >= PSI5_CHANNEL_CH_PMR_COUNT) + { + Psi5_Ip_axMessages[instance][Psi5ChannelId].psi5CurrentIndex = 0u; + } + else + { + Psi5_Ip_axMessages[instance][Psi5ChannelId].psi5CurrentIndex++; + } + + /*clear interrupt flag*/ + base->CHANNEL[Psi5ChannelId].CH_NDSR |= (uint32)((uint32)1u << (uint32)tempPosition); + } + + /* PSI5 Overwrite */ + if ((0u != base->CHANNEL[Psi5ChannelId].CH_OWSR) && (0u != (base->CHANNEL[Psi5ChannelId].CH_OWICR & PSI5_CH_OWICR_IE_OW_MASK))) + { + Events->Psi5_Psi5MessageOverwrite = TRUE; + + regRavlue = base->CHANNEL[Psi5ChannelId].CH_OWSR; + tempPosition = 0u; + + /* Iterate through bits of regRavlue till we find a set bit */ + while ((((regRavlue >> tempPosition) & 1u) == 0u) && (tempPosition < (PSI5_CHANNEL_CH_PMR_COUNT - 1u))) + { + /* increment position */ + tempPosition++; + } + + /*clear interrupt flag*/ + base->CHANNEL[Psi5ChannelId].CH_OWSR |= (uint32)((uint32)1u << (uint32)tempPosition); + } + + /* PSI5 error */ + if ((0u != base->CHANNEL[Psi5ChannelId].CH_EISR) && (0u != (base->CHANNEL[Psi5ChannelId].CH_EICR & PSI5_CH_EICR_IE_ERROR_MASK))) + { + Events->Psi5_Psi5MessageErrorsPresent = TRUE; + + regRavlue = base->CHANNEL[Psi5ChannelId].CH_EISR; + tempPosition = 0u; + + /* Iterate through bits of regRavlue till we find a set bit */ + while ((((regRavlue >> tempPosition) & 1u) == 0u) && (tempPosition < (PSI5_CHANNEL_CH_PMR_COUNT - 1u))) + { + /* increment position */ + tempPosition++; + } + + /*clear interrupt flag*/ + base->CHANNEL[Psi5ChannelId].CH_EISR |= (uint32)((uint32)1u << (uint32)tempPosition); + } + } +} + +/** + * + * Function Name : Psi5_Hw_GetEvents + * Description : Returns active events + * + *END**************************************************************************/ +static void Psi5_Hw_GetEvents(const Psi5_Ip_InstanceIdType Psi5InstanceId, + const Psi5_Ip_HwChannelIdType Psi5ChannelId, + Psi5_Ip_EventType *const Events + ) +{ + /* Enter critical region */ + SchM_Enter_Psi5_PSI5_EXCLUSIVE_AREA_05(); + + /* Tx events */ + Psi5_Hw_GetTxEvents(Psi5InstanceId, Psi5ChannelId, Events); + /* SMC events */ + Psi5_Hw_GetSmcEvents(Psi5InstanceId, Psi5ChannelId, Events); + /* PSI5 events */ + Psi5_Hw_GetPsi5Events(Psi5InstanceId, Psi5ChannelId, Events); + + /* Exit critical region*/ + SchM_Exit_Psi5_PSI5_EXCLUSIVE_AREA_05(); +} + +#if (STD_ON == PSI5_IP_GET_PSI5_FRAME_API) +/** + * + * Function Name : Psi5_Hw_GetRawPsi5Frame + * Description : Returns a raw PSI5 frame + * + */ +static Std_ReturnType Psi5_Hw_GetRawPsi5Frame(const Psi5_Ip_InstanceIdType instance, + const Psi5_Ip_HwChannelIdType Psi5ChannelId, + Psi5_Ip_RawFrameType *raw + ) +{ + PSI5_Type const * base = Psi5_Ip_axBaseAddresses[instance]; + uint8 msgPosition = PSI5_CHANNEL_CH_PMR_COUNT; + Std_ReturnType retVal; + + /* Enter critical region*/ + SchM_Enter_Psi5_PSI5_EXCLUSIVE_AREA_01(); + + if (0xFFu != Psi5_Ip_axMessages[instance][Psi5ChannelId].psi5CurrentIndex) + { + if (Psi5_Ip_axMessages[instance][Psi5ChannelId].psi5CurrentIndex > 0u) + { + Psi5_Ip_axMessages[instance][Psi5ChannelId].psi5CurrentIndex--; + + msgPosition = Psi5_Ip_axMessages[instance][Psi5ChannelId].psi5PosMsgAvailable[Psi5_Ip_axMessages[instance][Psi5ChannelId].psi5CurrentIndex]; + } + else if (0u == Psi5_Ip_axMessages[instance][Psi5ChannelId].psi5CurrentIndex) + { + msgPosition = Psi5_Ip_axMessages[instance][Psi5ChannelId].psi5PosMsgAvailable[Psi5_Ip_axMessages[instance][Psi5ChannelId].psi5CurrentIndex]; + + Psi5_Ip_axMessages[instance][Psi5ChannelId].psi5CurrentIndex = 0xFFu; + } + else + { + /* misra fix */ + } + + if (msgPosition < PSI5_CHANNEL_CH_PMR_COUNT) + { + /* Read message */ + (*raw)[0] = base->CHANNEL[Psi5ChannelId].CH_PMR[msgPosition].CH_PMRL; + (*raw)[1] = base->CHANNEL[Psi5ChannelId].CH_PMR[msgPosition].CH_PMRH; + + retVal = (Std_ReturnType)E_OK; + } + else + { + retVal = (Std_ReturnType)E_NOT_OK; + } + } + else + { + retVal = (Std_ReturnType)E_NOT_OK; + } + /* Exit critical region*/ + SchM_Exit_Psi5_PSI5_EXCLUSIVE_AREA_01(); + + return retVal; +} +#endif + +#if (STD_ON == PSI5_IP_GET_SMC_FRAME_API) +/** + * + * Function Name : Psi5_Hw_GetRawSmcFrame + * Description : Returns a raw SMC frame + * + */ +static Std_ReturnType Psi5_Hw_GetRawSmcFrame(const Psi5_Ip_InstanceIdType instance, + const Psi5_Ip_HwChannelIdType Psi5ChannelId, + Psi5_Ip_RawFrameType *raw + ) +{ + PSI5_MemMapPtr base = Psi5_Ip_axBaseAddresses[instance]; + uint8 msgPosition = PSI5_CHANNEL_CH_SFR_COUNT; + Std_ReturnType retVal; + + /* Enter critical region*/ + SchM_Enter_Psi5_PSI5_EXCLUSIVE_AREA_02(); + if (0xFFu != Psi5_Ip_axMessages[instance][Psi5ChannelId].smcCurrentIndex) + { + if (Psi5_Ip_axMessages[instance][Psi5ChannelId].smcCurrentIndex > 0u) + { + Psi5_Ip_axMessages[instance][Psi5ChannelId].smcCurrentIndex--; + + msgPosition = Psi5_Ip_axMessages[instance][Psi5ChannelId].smcPosMsgAvailable[Psi5_Ip_axMessages[instance][Psi5ChannelId].smcCurrentIndex]; + } + else if (0u == Psi5_Ip_axMessages[instance][Psi5ChannelId].smcCurrentIndex) + { + msgPosition = Psi5_Ip_axMessages[instance][Psi5ChannelId].smcPosMsgAvailable[Psi5_Ip_axMessages[instance][Psi5ChannelId].smcCurrentIndex]; + + Psi5_Ip_axMessages[instance][Psi5ChannelId].smcCurrentIndex = 0xFFu; + } + else + { + /* misra fix */ + } + + if (msgPosition < PSI5_CHANNEL_CH_SFR_COUNT) + { + /* Read message (only 32 bits in lower data buffer) */ + (*raw)[0] = base->CHANNEL[Psi5ChannelId].CH_SFR[msgPosition]; + + retVal = (Std_ReturnType)E_OK; + } + else + { + retVal = (Std_ReturnType)E_NOT_OK; + } + } + else + { + retVal = (Std_ReturnType)E_NOT_OK; + } + /* Exit critical region*/ + SchM_Exit_Psi5_PSI5_EXCLUSIVE_AREA_02(); + + return retVal; +} +#endif + +#if ((STD_ON == PSI5_IP_GET_PSI5_FRAME_API) || (STD_ON == PSI5_IP_DMA_PSI5_FRAME_IS_USED)) +/** + * + * Function Name : Psi5_Hw_ConvertRawPsi5Frame + * Description : Converts a raw PSI5 frame + * + */ +static void Psi5_Hw_ConvertRawPsi5Frame(Psi5_Ip_Psi5FrameType *frame, + Psi5_Ip_RawFrameType *raw, + const Psi5_Ip_SlotConfigType *states + ) +{ + frame->CRC = (uint8)(((*raw)[0] & PSI5_CH_PMRRL_CRC_MASK) >> PSI5_CH_PMRRL_CRC_SHIFT); + frame->C = (uint8)(((*raw)[0] & PSI5_CH_PMRRL_C_MASK) >> PSI5_CH_PMRRL_C_SHIFT); + frame->F = (uint8)(((*raw)[1] & PSI5_CH_PMRRH_F_MASK) >> PSI5_CH_PMRRH_F_SHIFT); + frame->EM = (uint8)(((*raw)[1] & PSI5_CH_PMRRH_EM_MASK) >> PSI5_CH_PMRRH_EM_SHIFT); + frame->E = (uint8)(((*raw)[1] & PSI5_CH_PMRRH_E_MASK) >> PSI5_CH_PMRRH_E_SHIFT); + frame->T = (uint8)(((*raw)[1] & PSI5_CH_PMRRH_T_MASK) >> PSI5_CH_PMRRH_T_SHIFT); + frame->SLOT_COUNTER = (uint8)(((*raw)[1] & PSI5_CH_PMRRH_SlotCounter_MASK) >> PSI5_CH_PMRRH_SlotCounter_SHIFT); + frame->TIME_STAMP = (uint32)(((*raw)[1] & PSI5_CH_PMRRH_TimeStampValue_MASK) >> PSI5_CH_PMRRH_TimeStampValue_SHIFT); + + /* If slot counter is 0 or any other out of range value, we assign settings from slot 1 (index 0) */ + uint32 slotIdx = (frame->SLOT_COUNTER < 1u) ? + 0u : (((frame->SLOT_COUNTER > PSI5_CHANNEL_CH_SFR_COUNT) ? + 5u : ((uint32)frame->SLOT_COUNTER - 1u))); + + /* 28 bits max, left aligned */ + uint32 dataRegion = (uint32)((*raw)[0] >> PSI5_CH_PMRRL_DATA_REGION_SHIFT); + + /* Number of normalization shifts */ + const uint8 shiftCount = (uint8)((uint8)PSI5_CH_PMRRL_DATA_REGION_WIDTH - (uint8)states[slotIdx].dataSize); + + /* If MSB first */ + if (states[slotIdx].msbFirst) + { + /* As we received it */ + frame->DATA_REGION = dataRegion >> shiftCount; + } + else + { + dataRegion = dataRegion >> shiftCount; + /* Reverse bits*/ + for (uint8 i = 0u; i < states[slotIdx].dataSize; i++) + { + if (0u != (dataRegion & (uint32)((uint32)1u << (uint32)i))) + { + frame->DATA_REGION |= (uint32)((uint32)1u << (uint32)((uint32)((uint32)states[slotIdx].dataSize - (uint32)1u) - (uint32)i)); + } + } + } +} +#endif + +#if ((STD_ON == PSI5_IP_GET_SMC_FRAME_API) || (STD_ON == PSI5_IP_DMA_SMC_FRAME_IS_USED)) +/** + * + * Function Name : Psi5_Hw_ConvertRawSmcFrame + * Description : Converts a raw SMC frame + * + */ +static void Psi5_Hw_ConvertRawSmcFrame(Psi5_Ip_SmcFrameType *frame, + Psi5_Ip_RawFrameType *raw + ) +{ + frame->SLOT_NO = (uint8)(((*raw)[0] & PSI5_CH_SFR_SLOT_NO_MASK) >> PSI5_CH_SFR_SLOT_NO_SHIFT); + frame->CER = (uint8)(((*raw)[0] & PSI5_CH_SFR_CER_MASK) >> PSI5_CH_SFR_CER_SHIFT); + frame->OW = (uint8)(((*raw)[0] & PSI5_CH_SFR_OW_MASK) >> PSI5_CH_SFR_OW_SHIFT); + frame->CRC = (uint8)(((*raw)[0] & PSI5_CH_SFR_CRC_MASK) >> PSI5_CH_SFR_CRC_SHIFT); + frame->C = (uint8)(((*raw)[0] & PSI5_CH_SFR_C_MASK) >> PSI5_CH_SFR_C_SHIFT); + frame->IDDATA = (uint8)(((*raw)[0] & PSI5_CH_SFR_IDDATA_MASK) >> PSI5_CH_SFR_IDDATA_SHIFT); + + /* Modify fields based on the C bit */ + if (0u != (frame->C)) + { + frame->ID = (uint8)(((*raw)[0] & PSI5_CH_SFR_ID_MASK) >> PSI5_CH_SFR_ID_SHIFT); + frame->DATA = (uint16)(((*raw)[0] & (PSI5_CH_SFR_IDDATA_MASK | PSI5_CH_SFR_DATA_MASK)) >> PSI5_CH_SFR_DATA_SHIFT); + } + else + { + frame->ID = (uint8)(((*raw)[0] & (PSI5_CH_SFR_ID_MASK | PSI5_CH_SFR_IDDATA_MASK)) >> PSI5_CH_SFR_IDDATA_SHIFT); + frame->DATA = (uint16)(((*raw)[0] & PSI5_CH_SFR_DATA_MASK) >> PSI5_CH_SFR_DATA_SHIFT); + } +} +#endif + +/** + * + * Function Name : Psi5_Hw_ConfigureSlot + * Description : Configures a single slot + * + */ +static void Psi5_Hw_ConfigureSlot(const Psi5_Ip_InstanceIdType instance, + const Psi5_Ip_HwChannelIdType Psi5ChannelId, + const Psi5_Ip_SlotConfigType *slot + ) +{ + PSI5_MemMapPtr base = Psi5_Ip_axBaseAddresses[instance]; + + switch(slot->slotId) + { + case 1u:{ base->CHANNEL[Psi5ChannelId].CH_S1SBR = PSI5_CH_S1SBR_S1SBT(slot->startOffs); break;} + case 2u:{ base->CHANNEL[Psi5ChannelId].CH_S2SBR = PSI5_CH_S2SBR_S2SBT(slot->startOffs); break;} + case 3u:{ base->CHANNEL[Psi5ChannelId].CH_S3SBR = PSI5_CH_S3SBR_S3SBT(slot->startOffs); break;} + case 4u:{ base->CHANNEL[Psi5ChannelId].CH_S4SBR = PSI5_CH_S4SBR_S4SBT(slot->startOffs); break;} + case 5u:{ base->CHANNEL[Psi5ChannelId].CH_S5SBR = PSI5_CH_S5SBR_S5SBT(slot->startOffs); break;} + case 6u:{ base->CHANNEL[Psi5ChannelId].CH_S6SBR = PSI5_CH_S6SBR_S6SBT(slot->startOffs); break;} + default: /*error, not possible by configuration */ break; + } + + /* Configuration */ + base->CHANNEL[Psi5ChannelId].CH_SFCR[slot->slotId - 1U] = PSI5_CH_SFCR_SLOT_EN(1u) | PSI5_CH_SFCR_TS_CAPT(((slot->tsCapS0 == FALSE) ? 0u : 1u)) | + PSI5_CH_SFCR_SMCL(((slot->hasSMC == FALSE) ? 0u : 1u)) | PSI5_CH_SFCR_DRL(slot->dataSize) | + PSI5_CH_SFCR_CRCP(((slot->hasParity == FALSE) ? 0u : 1u)); +} + +/** + * + * Function Name : Psi5_Hw_EnterConfigMode + * Description : Puts the channel in configuration mode + * + */ +static void Psi5_Hw_EnterConfigMode(const Psi5_Ip_InstanceIdType instance, + const Psi5_Ip_HwChannelIdType Psi5ChannelId + ) +{ + PSI5_MemMapPtr base = Psi5_Ip_axBaseAddresses[instance]; + + /* Configure channel */ + base->CHANNEL[Psi5ChannelId].CH_PCCR |= (PSI5_CH_PCCR_PSI5_CH_EN_MASK | PSI5_CH_PCCR_PSI5_CH_CONFIG_MASK); +} + +/** + * + * Function Name : Psi5_Hw_EnterNormalMode + * Description : Puts the channel in normal mode + * + */ +static void Psi5_Hw_EnterNormalMode(const Psi5_Ip_InstanceIdType instanceId, + const Psi5_Ip_HwChannelIdType Psi5ChannelId + ) +{ + + PSI5_MemMapPtr base = Psi5_Ip_axBaseAddresses[instanceId]; + + /* Configure channel */ + base->CHANNEL[Psi5ChannelId].CH_PCCR &= ~PSI5_CH_PCCR_PSI5_CH_CONFIG_MASK; +} + +/** + * + * Function Name : Psi5_Hw_ConfigureTx + * Description : Configures transmission + * + */ +static void Psi5_Hw_ConfigureTx(const Psi5_Ip_InstanceIdType instanceId, + const Psi5_Ip_ChannelConfigType *chCfg + ) +{ + PSI5_MemMapPtr base = Psi5_Ip_axBaseAddresses[instanceId]; + uint16 defaultSync = 0u; + + /* Set mode to synchronous */ + base->CHANNEL[chCfg->channelId].CH_PCCR |= PSI5_CH_PCCR_MODE_MASK; + + if (chCfg->txConfig->txDefault1) + { + defaultSync = 1u; + } + + /* Tx mode, Data length, default bit values, auto transfer from DBR to DSR */ + base->CHANNEL[chCfg->channelId].CH_DOBCR |= (PSI5_CH_DOBCR_CMD_TYPE(chCfg->txConfig->txMode) | PSI5_CH_DOBCR_DATA_LENGTH(((uint16)chCfg->txConfig->txSize) - ((uint16)1u)) + | PSI5_CH_DOBCR_DEFAULT_SYNC(defaultSync) + | (((chCfg->txConfig->txMode) == PSI5_TX_MODE_7) ? PSI5_CH_DOBCR_DSR_RST_MASK : PSI5_CH_DOBCR_DBR_RST_MASK) + | PSI5_CH_DOBCR_SW_READY_MASK); +} + +/** + * + * Function Name : Psi5_Hw_ConfigureRx + * Description : Configures reception + * + */ +static void Psi5_Hw_ConfigureRx(const Psi5_Ip_InstanceIdType instanceId, + const Psi5_Ip_ChannelConfigType *chCfg + ) +{ + PSI5_MemMapPtr base = Psi5_Ip_axBaseAddresses[instanceId]; + + /* Buffer size */ + base->CHANNEL[chCfg->channelId].CH_PCCR |= PSI5_CH_PCCR_MEM_DEPTH(((uint32)chCfg->rxConfig->rxBufSize) - ((uint32)1u)); + + /* bit rate */ + base->CHANNEL[chCfg->channelId].CH_PCCR |= PSI5_CH_PCCR_BIT_RATE(chCfg->rxConfig->bitRate); + + /* Fast clearing for both */ + base->CHANNEL[chCfg->channelId].CH_PCCR |= PSI5_CH_PCCR_FAST_CLR_PSI5_MASK | PSI5_CH_PCCR_FAST_CLR_SMC_MASK; +} + +/** + * + * Function Name : Psi5_Hw_ConfigurePulseGenerator + * Description : Configures pulse generation + * + */ +static void Psi5_Hw_ConfigurePulseGenerator(const Psi5_Ip_InstanceIdType instanceId, + const Psi5_Ip_ChannelConfigType *chCfg + ) +{ + PSI5_MemMapPtr base = Psi5_Ip_axBaseAddresses[instanceId]; + + /* CTC control */ + if (chCfg->txConfig->syncGlobal) + { + base->CHANNEL[chCfg->channelId].CH_PCCR |= PSI5_CH_PCCR_CTC_GED_SEL_MASK; + } + + /* GTM reset */ + if (chCfg->txConfig->asyncReset) + { + base->CHANNEL[chCfg->channelId].CH_PCCR |= PSI5_CH_PCCR_GTM_RESET_ASYNC_EN_MASK; + } + + /* Decoder offset */ + base->CHANNEL[chCfg->channelId].CH_MDDIS_OFF = chCfg->txConfig->decoderOffset; + + /* Sync states */ + if (((uint8)(chCfg->txConfig->syncState) & 4u) != 0u) + { + base->CHANNEL[chCfg->channelId].CH_DOBCR |= PSI5_CH_DOBCR_GTM_TRIG_SEL_MASK; + } + + if (((uint8)(chCfg->txConfig->syncState) & 2u) != 0u) + { + base->CHANNEL[chCfg->channelId].CH_DOBCR |= PSI5_CH_DOBCR_SP_PULSE_SEL_MASK; + } + + if (((uint8)(chCfg->txConfig->syncState) & 1u) != 0u) + { + base->CHANNEL[chCfg->channelId].CH_DOBCR |= PSI5_CH_DOBCR_OP_SEL_MASK; + } + + /* Pulse forming*/ + base->CHANNEL[chCfg->channelId].CH_PW0D = chCfg->txConfig->pulse0Width; + base->CHANNEL[chCfg->channelId].CH_PW1D = chCfg->txConfig->pulse1Width; + base->CHANNEL[chCfg->channelId].CH_CIPR = chCfg->txConfig->initialPulse; + base->CHANNEL[chCfg->channelId].CH_CTPR = chCfg->txConfig->targetPulse; +} + +#if (STD_ON == PSI5_IP_DMA_IS_USED) +/** + * + * Function Name : Psi5_Hw_ConfigureDma + * Description : Configures DMA + * + */ +static void Psi5_Hw_ConfigureDma(const Psi5_Ip_InstanceIdType instanceId, + const Psi5_Ip_ChannelConfigType *chCfg + ) +{ + PSI5_MemMapPtr base = Psi5_Ip_axBaseAddresses[instanceId]; + uint32 DCRvalue = 0; + Mcl_DmaChannelTransferListType global_Mcl_DmaChannelTransferList[11U]; + + const Psi5_Ip_ChannelRxPsi5DmaConfigType *psi5DmaConfig = chCfg->rxConfig->psi5DmaConfig; /*!< DMA config for PSI5 messages */ + const Psi5_Ip_ChannelRxSmcDmaConfigType *smcDmaConfig = chCfg->rxConfig->smcDmaConfig; /*!< DMA config for SMC messages */ + /* Pre - computed */ + boolean psi5DmaOk = psi5DmaConfig != NULL_PTR ? TRUE : FALSE; + boolean smcDmaOk = smcDmaConfig != NULL_PTR ? TRUE : FALSE; + + if (psi5DmaOk || smcDmaOk) + { + /* Create the desired configuration list. */ + global_Mcl_DmaChannelTransferList[0U].Param = MCL_DMA_CH_SET_SOURCE_ADDRESS; + /* Compiler_Warning: DMA TCD addresses are restricted to 32 bits, so casting from pointer type to uint32 is safe. + * The application should ensure that only addresses that fit in uint32 are used for configuring DMA. */ + global_Mcl_DmaChannelTransferList[1U].Param = MCL_DMA_CH_SET_DESTINATION_ADDRESS; + + global_Mcl_DmaChannelTransferList[2U].Param = MCL_DMA_CH_SET_DESTINATION_TRANSFER_SIZE; + global_Mcl_DmaChannelTransferList[2U].Value = (uint32)DMA_IP_TRANSFER_SIZE_4_BYTE; + global_Mcl_DmaChannelTransferList[3U].Param = MCL_DMA_CH_SET_SOURCE_TRANSFER_SIZE; + global_Mcl_DmaChannelTransferList[3U].Value = (uint32)DMA_IP_TRANSFER_SIZE_4_BYTE; + global_Mcl_DmaChannelTransferList[4U].Param = MCL_DMA_CH_SET_SOURCE_SIGNED_OFFSET; + global_Mcl_DmaChannelTransferList[4U].Value = (uint32)0U; + global_Mcl_DmaChannelTransferList[5U].Param = MCL_DMA_CH_SET_DESTINATION_SIGNED_OFFSET; + global_Mcl_DmaChannelTransferList[5U].Value = (uint32)4U; + global_Mcl_DmaChannelTransferList[6U].Param = MCL_DMA_CH_SET_SOURCE_MODULO; + global_Mcl_DmaChannelTransferList[6U].Value = (uint32)0U; + global_Mcl_DmaChannelTransferList[7U].Param = MCL_DMA_CH_SET_DESTINATION_MODULO; + global_Mcl_DmaChannelTransferList[7U].Value = (uint32)0U; + global_Mcl_DmaChannelTransferList[8U].Param = MCL_DMA_CH_SET_MINORLOOP_SIZE; + global_Mcl_DmaChannelTransferList[9U].Param = MCL_DMA_CH_SET_MAJORLOOP_COUNT; + global_Mcl_DmaChannelTransferList[9U].Value = (uint32)1U; + global_Mcl_DmaChannelTransferList[10U].Param = MCL_DMA_CH_SET_DESTINATION_SIGNED_LAST_ADDR_ADJ; + + /* Read DCR value */ + DCRvalue = base->CHANNEL[chCfg->channelId].CH_DCR; + /* Clear old value*/ + DCRvalue = DCRvalue & (~(PSI5_CH_DCR_DMA_PM_DS_WM_MASK | PSI5_CH_DCR_DMA_PM_DS_CONFIG_MASK | PSI5_CH_DCR_DMA_EN_SF_MASK)); + /* Set new value*/ + DCRvalue |= (psi5DmaOk ? (PSI5_CH_DCR_DMA_PM_DS_WM(psi5DmaConfig->psi5DmaWatermarkDmaTrigger - 1u)) : (uint32)0U); + DCRvalue |= (psi5DmaOk ? PSI5_CH_DCR_DMA_PM_DS_CONFIG(psi5DmaConfig->psi5DmaMode) : (uint32)0U); + DCRvalue |= (smcDmaOk ? (uint32)PSI5_CH_DCR_DMA_EN_SF_MASK : (uint32)0u); + /*Store value to register*/ + base->CHANNEL[chCfg->channelId].CH_DCR = DCRvalue; + + /* DMA transfer */ + if (smcDmaOk) + { + /*Source address: address of DSFR register */ + global_Mcl_DmaChannelTransferList[0U].Value = (uint32)(&base->CHANNEL[chCfg->channelId].CH_DSFR); + + /*Dest address: the address of internal buffer*/ + global_Mcl_DmaChannelTransferList[1U].Value = (uint32)(smcDmaConfig->smcDmaInternalBuffer); + + /*4 bytes transfer for each request*/ + global_Mcl_DmaChannelTransferList[8U].Value = (uint32)4U; + + /*Back to the start address of the buffer after finish transfer*/ + global_Mcl_DmaChannelTransferList[10U].Value = (uint32)(0xFFFFFFFF-sizeof(uint32)+1); + + /*Config and start DMA channel*/ + Mcl_SetDmaChannelTransferList(smcDmaConfig->smcDmaChannel, global_Mcl_DmaChannelTransferList, (uint32)11U); + Mcl_SetDmaChannelCommand(smcDmaConfig->smcDmaChannel, MCL_DMA_CH_START_REQUEST); + } + + if (psi5DmaOk) + { + if (PSI5_DMA_MODE_CONF4 == psi5DmaConfig->psi5DmaMode) + { + /* Mode CONF4: Only the diagnostic bits are transferred through the DDSR*/ + global_Mcl_DmaChannelTransferList[0U].Value = (uint32)(&base->CHANNEL[chCfg->channelId].CH_DDSR); + + /*Number of bytes for each request*/ + global_Mcl_DmaChannelTransferList[8U].Value = ((uint32)sizeof(Psi5_Ip_RawFrameType)); + + /*Back to the start address of the buffer after finish each transfer*/ + global_Mcl_DmaChannelTransferList[10U].Value = (uint32)(0xFFFFFFFF-sizeof(Psi5_Ip_RawFrameType)+1); + } + else if (PSI5_DMA_MODE_CONF3 == psi5DmaConfig->psi5DmaMode) + { + /* Mode CONF3: Data and diagnostic bits are transferred through the CH_DPMR*/ + global_Mcl_DmaChannelTransferList[0U].Value = (uint32)(&base->CHANNEL[chCfg->channelId].CH_DPMR); + + /*Number of bytes for each request*/ + global_Mcl_DmaChannelTransferList[8U].Value = ((uint32)sizeof(Psi5_Ip_RawFrameType)) * (psi5DmaConfig->psi5DmaWatermarkDmaTrigger); + + /*Back to the start address of the buffer after finish each transfer*/ + global_Mcl_DmaChannelTransferList[10U].Value = -(sint32)(sizeof(Psi5_Ip_RawFrameType) * (psi5DmaConfig->psi5DmaWatermarkDmaTrigger)); + } + else + { + /* Mode CONF2: Data and diagnostic bits are transferred through the CH_DPMR*/ + global_Mcl_DmaChannelTransferList[0U].Value = (uint32)(&base->CHANNEL[chCfg->channelId].CH_DPMR); + + /*Number of bytes for each request*/ + global_Mcl_DmaChannelTransferList[8U].Value = ((uint32)sizeof(Psi5_Ip_RawFrameType)) * (psi5DmaConfig->psi5DmaWatermarkDmaTrigger + 1U); + + /*Back to the start address of the buffer after finish each transfer*/ + global_Mcl_DmaChannelTransferList[10U].Value = -(sint32)(sizeof(Psi5_Ip_RawFrameType) * (psi5DmaConfig->psi5DmaWatermarkDmaTrigger + 1U)); + } + + /*Dest address the address of internal buffer*/ + global_Mcl_DmaChannelTransferList[1U].Value = (uint32)(psi5DmaConfig->psi5DmaInternalBuffer); + + /*Config and start DMA channel*/ + Mcl_SetDmaChannelTransferList(psi5DmaConfig->psi5DmaChannel, global_Mcl_DmaChannelTransferList, (uint32)11U); + Mcl_SetDmaChannelCommand(psi5DmaConfig->psi5DmaChannel, MCL_DMA_CH_START_REQUEST); + } + } +} +#endif + +/** + * + * Function Name : Psi5_Hw_InstanceDisable + * Description : Global channel disabler + * + */ +static void Psi5_Hw_InstanceDisable(const Psi5_Ip_InstanceIdType instanceId, + const boolean state + ) +{ + PSI5_MemMapPtr base = Psi5_Ip_axBaseAddresses[instanceId]; + + base->GCR = (uint16)(base->GCR & ~(uint16)PSI5_GCR_GLOBAL_DISABLE_REQ_MASK) | PSI5_GCR_GLOBAL_DISABLE_REQ(((FALSE == state) ? 0U : 1U)); +} + +/** + * + * Function Name : Psi5_Hw_StartGlobalCtc + * Description : Global CTC (timer) enabler. + * + */ +static Std_ReturnType Psi5_Hw_StartGlobalCtc(const Psi5_Ip_InstanceIdType instanceId, + const boolean state + ) +{ + Std_ReturnType ret = (Std_ReturnType)E_NOT_OK; + uint8 ChIndex; + PSI5_MemMapPtr base = Psi5_Ip_axBaseAddresses[instanceId]; + + for (ChIndex = 0u; ChIndex < PSI5_CHANNEL_COUNT; ChIndex++) + { + if ((base->CHANNEL[ChIndex].CH_PCCR & PSI5_CH_PCCR_CTC_GED_SEL_MASK) != 0U) + { + base->GCR = (uint16)(base->GCR & ~(uint16)PSI5_GCR_CTC_GED_MASK) | PSI5_GCR_CTC_GED(((FALSE == state) ? 0U : 1U)); + ret = (Std_ReturnType)E_OK; + } + } + + return ret; +} + +/** + * + * Function Name : Psi5_Hw_ResetRegisters + * Description : Resets registers + * + */ +static void Psi5_Hw_ResetRegisters(const Psi5_Ip_InstanceIdType instance) +{ + PSI5_MemMapPtr base = Psi5_Ip_axBaseAddresses[instance]; + uint8 ChIndex; + + for (ChIndex = 0u; ChIndex < PSI5_CHANNEL_COUNT; ChIndex++) + { + /* Control registers */ + base->CHANNEL[ChIndex].CH_DCR = 0u; + base->CHANNEL[ChIndex].CH_GICR = 0u; + base->CHANNEL[ChIndex].CH_NDICR = 0u; + base->CHANNEL[ChIndex].CH_OWICR = 0u; + base->CHANNEL[ChIndex].CH_EICR = 0u; + + /* Reset Slot configuration */ + base->CHANNEL[ChIndex].CH_S1SBR = 0u; + base->CHANNEL[ChIndex].CH_S2SBR = 0u; + base->CHANNEL[ChIndex].CH_S3SBR = 0u; + base->CHANNEL[ChIndex].CH_S4SBR = 0u; + base->CHANNEL[ChIndex].CH_S5SBR = 0u; + base->CHANNEL[ChIndex].CH_S6SBR = 0u; + + for (uint8 slotIdx = 0u; slotIdx < PSI5_CHANNEL_CH_SFR_COUNT; slotIdx++) + { + base->CHANNEL[ChIndex].CH_SFCR[slotIdx] = PSI5_CH_SFCR_DRL(8u); + } + + /* Boundary end */ + base->CHANNEL[ChIndex].CH_SNEBR = 0u; + + /* Tx block */ + base->CHANNEL[ChIndex].CH_DOBCR = 0u; + base->CHANNEL[ChIndex].CH_MDDIS_OFF = 0u; + base->CHANNEL[ChIndex].CH_PW0D = 0u; + base->CHANNEL[ChIndex].CH_PW1D = 0u; + base->CHANNEL[ChIndex].CH_CTPR = 0u; + base->CHANNEL[ChIndex].CH_CIPR = 0u; + + /* Normal and disable */ + base->CHANNEL[ChIndex].CH_PCCR = (PSI5_CH_PCCR_ERROR_SELECT0_MASK | PSI5_CH_PCCR_ERROR_SELECT1_MASK | + PSI5_CH_PCCR_ERROR_SELECT2_MASK | PSI5_CH_PCCR_ERROR_SELECT3_MASK | + PSI5_CH_PCCR_ERROR_SELECT4_MASK); + } +} + +#if ((STD_ON == PSI5_IP_GET_TRANSMISSION_STATUS_API) || (STD_ON == PSI5_IP_TRANSMIT_API)) +/** + * + * Function Name : Psi5_Hw_IsDataRegisterReady + * Description : Returns Tx register status + * + */ +static boolean Psi5_Hw_IsDataRegisterReady(const Psi5_Ip_InstanceIdType instance, + const Psi5_Ip_HwChannelIdType Psi5ChannelId + ) +{ + const uint8 arrayIndex = Psi5_Ip_pUsedConfig->instancesConfig[instance].chHwIdToIndexArrayConfig[Psi5ChannelId]; + const Psi5_Ip_ChannelConfigType *config = &(Psi5_Ip_pUsedConfig->instancesConfig[instance].channelConfig[arrayIndex]); + + boolean ret = FALSE; + + /* Depending on Tx type */ + if (NULL_PTR != config->txConfig) + { + if (PSI5_TX_MODE_7 == config->txConfig->txMode) + { + ret = (Psi5_Ip_axBaseAddresses[instance]->CHANNEL[Psi5ChannelId].CH_GISR & PSI5_CH_GISR_DSR_RDY_MASK) != 0u; + } + else + { + ret = (Psi5_Ip_axBaseAddresses[instance]->CHANNEL[Psi5ChannelId].CH_GISR & PSI5_CH_GISR_DPR_RDY_MASK) != 0u; + } + } + + return ret; +} +#endif + +/** + * + * Function Name : Psi5_EnterConfigMode + * Description : Enter CONFIG mode. + * + */ +static void Psi5_EnterConfigMode(const Psi5_Ip_InstanceType *instance) +{ + /* Disable the instance */ + Psi5_Hw_InstanceDisable(instance->instanceId, TRUE); + + /* Put all channels in configuration mode */ + for (uint8 chIdx = 0u; chIdx < instance->numOfChannels; chIdx++) + { + const Psi5_Ip_ChannelConfigType *chCfg = &instance->channelConfig[chIdx]; + + /* Enter configuration mode */ + Psi5_Hw_EnterConfigMode(instance->instanceId, chCfg->channelId); + } + + /* Enable the instance */ + Psi5_Hw_InstanceDisable(instance->instanceId, FALSE); +} + +/** + * + * Function Name : Psi5_EnterNormalMode + * Description : Enter NORMAL mode. + * + */ +static void Psi5_EnterNormalMode(const Psi5_Ip_InstanceType *instance) +{ + /* Put all channels in normal mode */ + for (uint32 chIdx = 0u; chIdx < instance->numOfChannels; chIdx++) + { + const Psi5_Ip_ChannelConfigType *chCfg = &instance->channelConfig[chIdx]; + + /* Enter normal mode */ + Psi5_Hw_EnterNormalMode(instance->instanceId, chCfg->channelId); + } +} + +/** + * + * Function Name : Psi5_ConfigureSlots + * Description : Configures a single slot. + * + */ +static void Psi5_ConfigureSlots(const Psi5_Ip_InstanceIdType instanceId, + const Psi5_Ip_ChannelConfigType *channelConfig + ) +{ + PSI5_MemMapPtr base = Psi5_Ip_axBaseAddresses[instanceId]; + const Psi5_Ip_SlotConfigType *lastSlotCfg = &(channelConfig->rxConfig->slotConfig[(channelConfig->rxConfig->numOfSlotConfigs - 1u)]); + uint16 SnEBT_Value = lastSlotCfg->startOffs + lastSlotCfg->slotLen; + uint8 LastSlotId = lastSlotCfg->slotId; + + /* For each slot configuration */ + for (uint32 slotIdx = 0u; slotIdx < channelConfig->rxConfig->numOfSlotConfigs; slotIdx++) + { + const Psi5_Ip_SlotConfigType *slotCfg = &(channelConfig->rxConfig->slotConfig[slotIdx]); + + /* Configure current slot */ + Psi5_Hw_ConfigureSlot(instanceId, channelConfig->channelId, slotCfg); + } + + /* New time frame */ + base->CHANNEL[channelConfig->channelId].CH_SNEBR = PSI5_CH_SNEBR_SnEBT(SnEBT_Value) | PSI5_CH_SNEBR_SLOT_NO(LastSlotId); +} + +/** + * + * Function Name : Psi5_ConfigureChannel + * Description : Configures a single channel. + * + */ +static void Psi5_ConfigureChannel(const Psi5_Ip_InstanceIdType instanceId, + const Psi5_Ip_ChannelConfigType *chCfg + ) +{ + PSI5_MemMapPtr base = Psi5_Ip_axBaseAddresses[instanceId]; + + /* Set debug mode */ + base->CHANNEL[chCfg->channelId].CH_PCCR |= PSI5_CH_PCCR_DEBUG_EN(((chCfg->debugEnable == TRUE) ? 1u : 0u)) | PSI5_CH_PCCR_DEBUG_FREEZE_CTRL(((chCfg->debugFreeze == TRUE) ? 1u : 0u)); + + /* Configure Rx parameters */ + Psi5_Hw_ConfigureRx(instanceId, chCfg); + +#if (STD_ON == PSI5_IP_DMA_IS_USED) + /* Configure DMA */ + Psi5_Hw_ConfigureDma(instanceId, chCfg); +#endif + + /* Configure the Tx side */ + if (PSI5_SYNCHRONOUS == chCfg->channelMode) + { + /* Configure Tx mode */ + Psi5_Hw_ConfigureTx(instanceId, chCfg); + + /* Configure the pulse generator */ + Psi5_Hw_ConfigurePulseGenerator(instanceId, chCfg); + } + + /* Configure interrupts */ + Psi5_Hw_EnableInterrupts(instanceId, chCfg, TRUE); +} + +/** + * + * Function Name : Psi5_ConfigureChannels + * Description : Configures all the channels. + * + */ +static void Psi5_ConfigureChannels(const Psi5_Ip_InstanceType *instance) +{ + /* For each channel configuration */ + for (uint32 chIdx = 0u; chIdx < instance->numOfChannels; chIdx++) + { + const Psi5_Ip_ChannelConfigType *chCfg = &(instance->channelConfig[chIdx]); + + /* Configure the pulse generator */ + Psi5_ConfigureChannel(instance->instanceId, chCfg); + + /* Configure the slots */ + Psi5_ConfigureSlots(instance->instanceId, chCfg); + } + + /* Global Sync start */ + (void)Psi5_Hw_StartGlobalCtc(instance->instanceId, instance->globalCtcEn); +} + +/** + * + * Function Name : Psi5_Hw_EnableInterrupts + * Description : Interrupt enabler + * + */ +static void Psi5_Hw_EnableInterrupts(const Psi5_Ip_InstanceIdType instance, + const Psi5_Ip_ChannelConfigType *chCfg, + const boolean Enable + ) +{ + PSI5_MemMapPtr base = Psi5_Ip_axBaseAddresses[instance]; + const uint8 arrayIndex = Psi5_Ip_pUsedConfig->instancesConfig[instance].chHwIdToIndexArrayConfig[chCfg->channelId]; + const Psi5_Ip_ChannelConfigType *config = &(Psi5_Ip_pUsedConfig->instancesConfig[instance].channelConfig[arrayIndex]); + const Psi5_Ip_ErrorSelectConfigType *errorSelect = config->errorSelectConfig; + uint32 ErrorSelectBits; + + /* Clear interrupts flag */ + Psi5_Hw_ClearEvents(instance, chCfg->channelId); + /* We need to enable ALL interrupts */ + if (Enable != (boolean)FALSE) + { + ErrorSelectBits = (uint32)((((errorSelect->errorSelect0 == FALSE) ? (uint32)0u : (uint32)1u) << PSI5_CH_PCCR_ERROR_SELECT0_SHIFT) | + (((errorSelect->errorSelect1 == FALSE) ? (uint32)0u : (uint32)1u) << PSI5_CH_PCCR_ERROR_SELECT1_SHIFT) | + (((errorSelect->errorSelect2 == FALSE) ? (uint32)0u : (uint32)1u) << PSI5_CH_PCCR_ERROR_SELECT2_SHIFT) | + (((errorSelect->errorSelect3 == FALSE) ? (uint32)0u : (uint32)1u) << PSI5_CH_PCCR_ERROR_SELECT3_SHIFT) | + (((errorSelect->errorSelect4 == FALSE) ? (uint32)0u : (uint32)1u) << PSI5_CH_PCCR_ERROR_SELECT4_SHIFT)); + } + else + { + ErrorSelectBits = 0U; + } + + /* Error interrupts */ + base->CHANNEL[chCfg->channelId].CH_PCCR |= ErrorSelectBits; + +#if (STD_ON == PSI5_IP_DMA_PSI5_FRAME_IS_USED) + /* DMA interrupts (Only if DMA enabled) */ + if (NULL_PTR != chCfg->rxConfig->psi5DmaConfig) + { + base->CHANNEL[chCfg->channelId].CH_DCR = Enable ? base->CHANNEL[chCfg->channelId].CH_DCR | (PSI5_CH_DCR_IE_DMA_TF_PM_DS_MASK | PSI5_CH_DCR_IE_DMA_PM_DS_FIFO_FULL_MASK | PSI5_CH_DCR_IE_DMA_PM_DS_UF_MASK) : base->CHANNEL[chCfg->channelId].CH_DCR & ~(PSI5_CH_DCR_IE_DMA_TF_PM_DS_MASK | PSI5_CH_DCR_IE_DMA_PM_DS_FIFO_FULL_MASK | PSI5_CH_DCR_IE_DMA_PM_DS_UF_MASK); + + /*Disable all RX interrupts*/ + base->CHANNEL[chCfg->channelId].CH_NDICR = 0U; + base->CHANNEL[chCfg->channelId].CH_OWICR = 0U; + base->CHANNEL[chCfg->channelId].CH_EICR = 0U; + + } + else +#endif + { + /*Enable PSI5 Rx interrupts */ + base->CHANNEL[chCfg->channelId].CH_NDICR = Enable ? PSI5_CH_NDICR_IE_ND(chCfg->rxConfig->watermarkInterruptLevel) : 0U; + base->CHANNEL[chCfg->channelId].CH_OWICR = Enable ? PSI5_CH_OWICR_IE_OW(chCfg->rxConfig->watermarkInterruptLevel) : 0U; + base->CHANNEL[chCfg->channelId].CH_EICR = Enable ? PSI5_CH_EICR_IE_ERROR(chCfg->rxConfig->watermarkInterruptLevel) : 0U; + } + +#if (STD_ON == PSI5_IP_DMA_SMC_FRAME_IS_USED) + if (NULL_PTR != chCfg->rxConfig->smcDmaConfig) + { + base->CHANNEL[chCfg->channelId].CH_DCR = Enable ? base->CHANNEL[chCfg->channelId].CH_DCR | (PSI5_CH_DCR_IE_DMA_TF_SF_MASK | PSI5_CH_DCR_IE_DMA_SFUF_MASK) : base->CHANNEL[chCfg->channelId].CH_DCR & ~(PSI5_CH_DCR_IE_DMA_TF_SF_MASK | PSI5_CH_DCR_IE_DMA_SFUF_MASK); + } +#endif + +} + +/** + * + * Function Name : Psi5_Hw_ClearEvents + * Description : Clears all active events + * + */ +static void Psi5_Hw_ClearEvents(const Psi5_Ip_InstanceIdType Psi5InstanceId, + const Psi5_Ip_HwChannelIdType Psi5ChannelId + ) +{ + PSI5_MemMapPtr base = Psi5_Ip_axBaseAddresses[Psi5InstanceId]; + +#if (STD_ON == PSI5_IP_DMA_IS_USED) + uint32 Ch_Dsr_Value = 0; + +#if (STD_ON == PSI5_IP_DMA_PSI5_FRAME_IS_USED) + Ch_Dsr_Value = PSI5_CH_DSR_IS_DMA_PM_DS_FIFO_FULL_MASK | PSI5_CH_DSR_IS_DMA_TF_PM_DS_MASK | PSI5_CH_DSR_IS_DMA_PM_DS_UF_MASK; +#endif + +#if (STD_ON == PSI5_IP_DMA_SMC_FRAME_IS_USED) + Ch_Dsr_Value |= PSI5_CH_DSR_IS_DMA_TF_SF_MASK | PSI5_CH_DSR_IS_DMA_SFUF_MASK; +#endif + + /* DMA flags */ + base->CHANNEL[Psi5ChannelId].CH_DSR = Ch_Dsr_Value; +#endif + + /* General flags */ + base->CHANNEL[Psi5ChannelId].CH_GISR = PSI5_CH_GISR_IS_CESM_MASK | PSI5_CH_GISR_IS_STS_MASK + | PSI5_CH_GISR_IS_DTS_MASK | PSI5_CH_GISR_IS_DSROW_MASK + | PSI5_CH_GISR_IS_BROW_MASK | PSI5_CH_GISR_IS_PROW_MASK + | PSI5_CH_GISR_IS_OWSM_MASK | PSI5_CH_GISR_IS_NVSM_MASK; + + /* PSI5 status */ + base->CHANNEL[Psi5ChannelId].CH_NDSR = PSI5_CH_NDSR_NDS_MASK; + base->CHANNEL[Psi5ChannelId].CH_OWSR = PSI5_CH_OWSR_OWS_MASK; + base->CHANNEL[Psi5ChannelId].CH_EISR = PSI5_CH_EISR_ERROR_MASK; +} + +/** + * + * Function Name : Psi5_Ip_IRQ_Handler + * Description : Gets called from the low level handler with instance and channel as parameter. + * + */ +void Psi5_Ip_IRQ_Handler(const Psi5_Ip_InstanceIdType Psi5InstanceId, + const Psi5_Ip_HwChannelIdType Psi5ChannelId + ) +{ + Psi5_Ip_EventType Events; + + /*Clear all values*/ + Events.Psi5_Psi5MessageReceived = FALSE; + Events.Psi5_Psi5MessageOverwrite = FALSE; + Events.Psi5_Psi5MessageErrorsPresent = FALSE; + Events.Psi5_SmcMessageReceived = FALSE; + Events.Psi5_SmcMessageOverwrite = FALSE; + Events.Psi5_SmcMessageCRCError = FALSE; + Events.Psi5_TxDataOverwrite = FALSE; + Events.Psi5_DriverReadyToTransmit = FALSE; + Events.Psi5_Psi5DmaOverflow = FALSE; + Events.Psi5_Psi5DmaUnderflow = FALSE; + Events.Psi5_Psi5DmaTransferComplete = FALSE; + Events.Psi5_SmcDmaUnderflow = FALSE; + Events.Psi5_SmcDmaTransferComplete = FALSE; + + Psi5_Hw_GetEvents(Psi5InstanceId, Psi5ChannelId, &Events); + + if(TRUE == Psi5_Ip_bDriverInitialized) + { + const uint8 arrayIndex = Psi5_Ip_pUsedConfig->instancesConfig[Psi5InstanceId].chHwIdToIndexArrayConfig[Psi5ChannelId]; + const Psi5_Ip_ChannelConfigType * chCfg = &(Psi5_Ip_pUsedConfig->instancesConfig[Psi5InstanceId].channelConfig[arrayIndex]); + + if(NULL_PTR != chCfg->callback) + { + chCfg->callback(Events); + } + } +} + +/** + * + * Function Name : Psi5_Ip_Init + * Description : Initializes the driver for a given peripheral + * according to the given configuration structure. + * + * Implements : Psi5_Ip_Init_Activity + */ +void Psi5_Ip_Init(const Psi5_Ip_ConfigType *configPtr) +{ + uint8 instanceCnt = 0u; + uint8 channelCnt = 0u; + Psi5_Ip_pUsedConfig = configPtr; + Psi5_Ip_bDriverInitialized = TRUE; + + for (instanceCnt = 0u; instanceCnt < PSI5_INSTANCE_COUNT; instanceCnt++) + { + for (channelCnt = 0u; channelCnt < PSI5_CHANNEL_COUNT; channelCnt++) + { + Psi5_Ip_axMessages[instanceCnt][channelCnt].psi5CurrentIndex = 0xFFu; + Psi5_Ip_axMessages[instanceCnt][channelCnt].smcCurrentIndex = 0xFFu; + } + } + + for (instanceCnt = 0u; instanceCnt < Psi5_Ip_pUsedConfig->numOfInstances; instanceCnt++) + { + const Psi5_Ip_InstanceType *cfgInstance = &(Psi5_Ip_pUsedConfig->instancesConfig[instanceCnt]); + /* Enter configuration mode */ + Psi5_EnterConfigMode(cfgInstance); + + /* Configure channels */ + Psi5_ConfigureChannels(cfgInstance); + + /* Enter normal mode */ + Psi5_EnterNormalMode(cfgInstance); + } +} + +#if (STD_ON == PSI5_IP_GET_PSI5_FRAME_API) +/** + * + * Function Name : Psi5_Ip_GetPsi5Frame + * Description : Returns the last received PSI5 frame. + * + * Implements : Psi5_Ip_GetPsi5Frame_Activity + */ +Std_ReturnType Psi5_Ip_GetPsi5Frame(const Psi5_Ip_InstanceIdType Psi5InstanceId, + const Psi5_Ip_HwChannelIdType Psi5ChannelId, + Psi5_Ip_Psi5FrameType *PsiFramePtr + ) +{ + Std_ReturnType ret; + Psi5_Ip_RawFrameType Psi5_RawFrame; + const uint8 arrayIndex = Psi5_Ip_pUsedConfig->instancesConfig[Psi5InstanceId].chHwIdToIndexArrayConfig[Psi5ChannelId]; + const Psi5_Ip_ChannelConfigType *config = &(Psi5_Ip_pUsedConfig->instancesConfig[Psi5InstanceId].channelConfig[arrayIndex]); + + ret = Psi5_Hw_GetRawPsi5Frame(Psi5InstanceId, Psi5ChannelId, &Psi5_RawFrame); + + if ((Std_ReturnType)E_OK == ret) + { + const Psi5_Ip_SlotConfigType *slotStates = config->rxConfig->slotConfig; + + Psi5_Hw_ConvertRawPsi5Frame(PsiFramePtr, &Psi5_RawFrame, slotStates); + } + + return ret; +} +#endif + +#if (STD_ON == PSI5_IP_GET_SMC_FRAME_API) +/** + * + * Function Name : Psi5_Ip_GetSmcFrame + * Description : Returns the last received SMC frame. + * + * Implements : Psi5_Ip_GetSmcFrame_Activity + */ +Std_ReturnType Psi5_Ip_GetSmcFrame(const Psi5_Ip_InstanceIdType Psi5InstanceId, + const Psi5_Ip_HwChannelIdType Psi5ChannelId, + Psi5_Ip_SmcFrameType *Psi5SmcFramePtr + ) +{ + Std_ReturnType ret; + Psi5_Ip_RawFrameType Psi5_RawFrame; + + ret = Psi5_Hw_GetRawSmcFrame(Psi5InstanceId, Psi5ChannelId, &Psi5_RawFrame); + + if (ret == (Std_ReturnType)E_OK) + { + Psi5_Hw_ConvertRawSmcFrame(Psi5SmcFramePtr, &Psi5_RawFrame); + } + + return ret; +} +#endif + +/** + * + * Function Name : Psi5_Ip_DeInit + * Description : Stops the driver and resets the internal states. + * + * Implements : Psi5_Ip_DeInit_Activity + */ +void Psi5_Ip_DeInit(void) +{ + uint8 instanceCnt; + + Psi5_Ip_bDriverInitialized = FALSE; + + for (instanceCnt = 0u; instanceCnt < Psi5_Ip_pUsedConfig->numOfInstances; instanceCnt++) + { + /* Put all channels in configuration mode */ + for (uint8 chIdx = 0u; chIdx < Psi5_Ip_pUsedConfig->instancesConfig[instanceCnt].numOfChannels; chIdx++) + { + const Psi5_Ip_ChannelConfigType *chCfg = &(Psi5_Ip_pUsedConfig->instancesConfig[instanceCnt].channelConfig[chIdx]); + + /* Disable the instance */ + Psi5_Hw_InstanceDisable(Psi5_Ip_pUsedConfig->instancesConfig[instanceCnt].instanceId, TRUE); + + /* Enter configuration mode */ + Psi5_Hw_EnterConfigMode(Psi5_Ip_pUsedConfig->instancesConfig[instanceCnt].instanceId, chCfg->channelId); + + /* Enable the instance */ + Psi5_Hw_InstanceDisable(Psi5_Ip_pUsedConfig->instancesConfig[instanceCnt].instanceId, FALSE); + + /* Disable interrupts */ + Psi5_Hw_EnableInterrupts(Psi5_Ip_pUsedConfig->instancesConfig[instanceCnt].instanceId, chCfg, FALSE); + + Psi5_Hw_ClearEvents(Psi5_Ip_pUsedConfig->instancesConfig[instanceCnt].instanceId, chIdx); + } + + (void)Psi5_Hw_StartGlobalCtc(Psi5_Ip_pUsedConfig->instancesConfig[instanceCnt].instanceId, FALSE); + + /* Clear all registers */ + Psi5_Hw_ResetRegisters(Psi5_Ip_pUsedConfig->instancesConfig[instanceCnt].instanceId); + + /* Disable the instance */ + Psi5_Hw_InstanceDisable(Psi5_Ip_pUsedConfig->instancesConfig[instanceCnt].instanceId, TRUE); + } + + Psi5_Ip_pUsedConfig = NULL_PTR; +} + +#if (STD_ON == PSI5_IP_TRANSMIT_API) +/** + * + * Function Name : Psi5_Ip_Transmit + * Description : Transmits a frame (standard or custom). + * + * Implements : Psi5_Ip_Transmit_Activity + */ +Std_ReturnType Psi5_Ip_Transmit(const Psi5_Ip_InstanceIdType Psi5InstanceId, + const Psi5_Ip_HwChannelIdType Psi5ChannelId, + const uint64 Psi5Data + ) +{ + Std_ReturnType ret; + + const uint8 arrayIndex = Psi5_Ip_pUsedConfig->instancesConfig[Psi5InstanceId].chHwIdToIndexArrayConfig[Psi5ChannelId]; + const Psi5_Ip_ChannelConfigType *config = &(Psi5_Ip_pUsedConfig->instancesConfig[Psi5InstanceId].channelConfig[arrayIndex]); + + /* Only if enabled */ + if (NULL_PTR != config->txConfig) + { + /* Check if ready for Tx */ + if (!Psi5_Hw_IsDataRegisterReady(Psi5InstanceId, Psi5ChannelId)) + { + ret = (Std_ReturnType)E_NOT_OK; + } + else + { + /* Write and trigger */ + PSI5_MemMapPtr base = Psi5_Ip_axBaseAddresses[Psi5InstanceId]; + + /* Enter critical region*/ + SchM_Enter_Psi5_PSI5_EXCLUSIVE_AREA_00(); + + if (PSI5_TX_MODE_7 == config->txConfig->txMode) + { + base->CHANNEL[Psi5ChannelId].CH_DSRH = (uint32)((Psi5Data >> 32u) & PSI5_CH_DSRH_DSR_MASK); + base->CHANNEL[Psi5ChannelId].CH_DSRL = (uint32)(Psi5Data & PSI5_CH_DSRL_DSR_MASK); + base->CHANNEL[Psi5ChannelId].CH_GISR |= PSI5_CH_GISR_DSR_RDY_MASK; + /* Tx interrupts */ + if ((NULL_PTR != config->callback) && ((PSI5_SYNC_STATE_2 == config->txConfig->syncState) || (PSI5_SYNC_STATE_4 == config->txConfig->syncState))) + { + base->CHANNEL[Psi5ChannelId].CH_GICR |= (PSI5_CH_GICR_IE_DSROW_MASK | PSI5_CH_GICR_IE_DSRR_MASK); + } + } + else + { + base->CHANNEL[Psi5ChannelId].CH_DPRL = (uint32)(Psi5Data & PSI5_CH_DPRL_DPR_MASK); + base->CHANNEL[Psi5ChannelId].CH_GISR |= PSI5_CH_GISR_DPR_RDY_MASK; + /* Tx interrupts */ + if ((NULL_PTR != config->callback) && ((PSI5_SYNC_STATE_2 == config->txConfig->syncState) || (PSI5_SYNC_STATE_4 == config->txConfig->syncState))) + { + base->CHANNEL[Psi5ChannelId].CH_GICR |= (PSI5_CH_GICR_IE_PROW_MASK | PSI5_CH_GICR_IE_PRR_MASK); + } + } + /* Exit critical region*/ + SchM_Exit_Psi5_PSI5_EXCLUSIVE_AREA_00(); + ret = (Std_ReturnType)E_OK; + } + } + else + { + ret = (Std_ReturnType)E_NOT_OK; + } + + return ret; +} +#endif + +#if (STD_ON == PSI5_IP_GET_TRANSMISSION_STATUS_API) +/** + * + * Function Name : Psi5_Ip_GetTransmissionStatus + * Description : Returns the status of the transmission part of the driver. + * + * Implements : Psi5_Ip_GetTransmissionStatus_Activity + */ +boolean Psi5_Ip_GetTransmissionStatus(const Psi5_Ip_InstanceIdType Psi5InstanceId, + const Psi5_Ip_HwChannelIdType Psi5ChannelId + ) +{ + /* Status */ + return Psi5_Hw_IsDataRegisterReady(Psi5InstanceId, Psi5ChannelId); +} +#endif + +#if (STD_ON == PSI5_IP_SET_GLOBAL_SYNC_API) +/** + * + * Function Name : Psi5_Ip_SetGlobalSync + * Description : Sets the global Pulse Generator state. + * + * Implements : Psi5_Ip_SetGlobalSync_Activity + */ +Std_ReturnType Psi5_Ip_SetGlobalSync(const uint8 Psi5InstanceId, + const boolean PsiState + ) +{ + Std_ReturnType retVal; + /* Enter critical region */ + SchM_Enter_Psi5_PSI5_EXCLUSIVE_AREA_03(); + + retVal = Psi5_Hw_StartGlobalCtc((Psi5InstanceId == 0U) ? PSI5_INSTANCE0 : PSI5_INSTANCE1, PsiState); + + /* Exit critical region*/ + SchM_Exit_Psi5_PSI5_EXCLUSIVE_AREA_03(); + + return retVal; +} +#endif + +#if (STD_ON == PSI5_IP_SET_CHANNEL_SYNC_API) +/** + * + * Function Name : Psi5_Ip_SetChannelSync + * Description : Sets the local (Psi5ChannelId) Pulse Generator state. + * + * Implements : Psi5_Ip_SetChannelSync_Activity + */ +Std_ReturnType Psi5_Ip_SetChannelSync(const Psi5_Ip_InstanceIdType Psi5InstanceId, + const Psi5_Ip_HwChannelIdType Psi5ChannelId, + const boolean PsiState + ) +{ + Std_ReturnType ret = (Std_ReturnType)E_NOT_OK; + /* Enable the local CTC */ + PSI5_MemMapPtr base = Psi5_Ip_axBaseAddresses[Psi5InstanceId]; + + /* Enter critical region */ + SchM_Enter_Psi5_PSI5_EXCLUSIVE_AREA_04(); + + if (0u == (base->CHANNEL[Psi5ChannelId].CH_PCCR & PSI5_CH_PCCR_CTC_GED_SEL_MASK)) + { + base->CHANNEL[Psi5ChannelId].CH_PCCR = PsiState ? (base->CHANNEL[Psi5ChannelId].CH_PCCR | PSI5_CH_PCCR_CTC_ED_MASK) : (base->CHANNEL[Psi5ChannelId].CH_PCCR & ~PSI5_CH_PCCR_CTC_ED_MASK); + + ret = (Std_ReturnType)E_OK; + } + + /* Exit critical region*/ + SchM_Exit_Psi5_PSI5_EXCLUSIVE_AREA_04(); + + return ret; +} +#endif + +#define PSI5_STOP_SEC_CODE +#include "Psi5_MemMap.h" + +#ifdef __cplusplus +} +#endif + +/** @} */ diff --git a/s32/drivers/s32ze/Psi5/src/Psi5_Ip_Irq.c b/s32/drivers/s32ze/Psi5/src/Psi5_Ip_Irq.c new file mode 100644 index 000000000..c23d063e2 --- /dev/null +++ b/s32/drivers/s32ze/Psi5/src/Psi5_Ip_Irq.c @@ -0,0 +1,204 @@ +/* + * Copyright 2021-2024 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/** +* @file Psi5_Ip_Irq.c +* +* @addtogroup PSI5_IP PSI5 IPV Driver +* @{ +*/ + + +#ifdef __cplusplus +extern "C"{ +#endif + +/*================================================================================================== +* INCLUDE FILES +* 1) system and project includes +* 2) needed interfaces from external units +* 3) internal and external interfaces from this unit +==================================================================================================*/ + +#include "Psi5_Ip.h" +#include "Psi5_Ip_Irq.h" + +/*================================================================================================== +* SOURCE FILE VERSION INFORMATION +==================================================================================================*/ +#define PSI5_IP_IRQ_VENDOR_ID_C 43 +#define PSI5_IP_IRQ_AR_RELEASE_MAJOR_VERSION_C 4 +#define PSI5_IP_IRQ_AR_RELEASE_MINOR_VERSION_C 7 +#define PSI5_IP_IRQ_AR_RELEASE_REVISION_VERSION_C 0 +#define PSI5_IP_IRQ_SW_MAJOR_VERSION_C 2 +#define PSI5_IP_IRQ_SW_MINOR_VERSION_C 0 +#define PSI5_IP_IRQ_SW_PATCH_VERSION_C 0 + +/*================================================================================================== +* FILE VERSION CHECKS +==================================================================================================*/ + +/* Checks against Psi5_Ip.h */ +#if (PSI5_IP_IRQ_VENDOR_ID_C != PSI5_IP_VENDOR_ID) + #error "Psi5_Ip_Irq.c and Psi5_Ip.h have different vendor ids" +#endif +#if ((PSI5_IP_IRQ_AR_RELEASE_MAJOR_VERSION_C != PSI5_IP_AR_RELEASE_MAJOR_VERSION) || \ + (PSI5_IP_IRQ_AR_RELEASE_MINOR_VERSION_C != PSI5_IP_AR_RELEASE_MINOR_VERSION) || \ + (PSI5_IP_IRQ_AR_RELEASE_REVISION_VERSION_C != PSI5_IP_AR_RELEASE_REVISION_VERSION) \ + ) + #error "AUTOSAR Version Numbers of Psi5_Ip_Irq.c and Psi5_Ip.h are different" +#endif +#if ((PSI5_IP_IRQ_SW_MAJOR_VERSION_C != PSI5_IP_SW_MAJOR_VERSION) || \ + (PSI5_IP_IRQ_SW_MINOR_VERSION_C != PSI5_IP_SW_MINOR_VERSION) || \ + (PSI5_IP_IRQ_SW_PATCH_VERSION_C != PSI5_IP_SW_PATCH_VERSION) \ + ) + #error "Software Version Numbers of Psi5_Ip_Irq.c and Psi5_Ip.h are different" +#endif + +/* Checks against Psi5_Ip_Irq.h */ +#if (PSI5_IP_IRQ_VENDOR_ID_C != PSI5_IP_IRQ_VENDOR_ID) + #error "Psi5_Ip_Irq.c and Psi5_Ip_Irq.h have different vendor ids" +#endif +#if ((PSI5_IP_IRQ_AR_RELEASE_MAJOR_VERSION_C != PSI5_IP_IRQ_AR_RELEASE_MAJOR_VERSION) || \ + (PSI5_IP_IRQ_AR_RELEASE_MINOR_VERSION_C != PSI5_IP_IRQ_AR_RELEASE_MINOR_VERSION) || \ + (PSI5_IP_IRQ_AR_RELEASE_REVISION_VERSION_C != PSI5_IP_IRQ_AR_RELEASE_REVISION_VERSION) \ + ) + #error "AUTOSAR Version Numbers of Psi5_Ip_Irq.c and Psi5_Ip_Irq.h are different" +#endif +#if ((PSI5_IP_IRQ_SW_MAJOR_VERSION_C != PSI5_IP_IRQ_SW_MAJOR_VERSION) || \ + (PSI5_IP_IRQ_SW_MINOR_VERSION_C != PSI5_IP_IRQ_SW_MINOR_VERSION) || \ + (PSI5_IP_IRQ_SW_PATCH_VERSION_C != PSI5_IP_IRQ_SW_PATCH_VERSION) \ + ) + #error "Software Version Numbers of Psi5_Ip_Irq.c and Psi5_Ip_Irq.h are different" +#endif + +/*================================================================================================== +* LOCAL MACROS +==================================================================================================*/ + +/*================================================================================================== +* LOCAL TYPEDEFS (STRUCTURES, UNIONS, ENUMS) +==================================================================================================*/ + +/*================================================================================================== +* LOCAL CONSTANTS +==================================================================================================*/ + +/*================================================================================================== +* LOCAL VARIABLES +==================================================================================================*/ + +/*================================================================================================== +* GLOBAL CONSTANTS +==================================================================================================*/ + +#define PSI5_START_SEC_CODE +#include "Psi5_MemMap.h" + +#ifdef PSI5_IP_ENABLE_INTERRUPTS_PSI5_0_CH0 +/** + * + * Function Name : Psi5_IRQ_Handle_PSI5_0_CH0 + * Description : Must be mapped to the generic interrupt of instace 0 channel 0. + */ +ISR(Psi5_IRQ_Handle_PSI5_0_CH0) +{ + Psi5_Ip_IRQ_Handler(PSI5_INSTANCE0, PSI5_0_CH0); +} +#endif + +#ifdef PSI5_IP_ENABLE_INTERRUPTS_PSI5_0_CH1 +/** + * + * Function Name : Psi5_IRQ_Handle_PSI5_0_CH0 + * Description : Must be mapped to the generic interrupt of instace 0 channel 1. + */ +ISR(Psi5_IRQ_Handle_PSI5_0_CH1) +{ + Psi5_Ip_IRQ_Handler(PSI5_INSTANCE0, PSI5_0_CH1); +} +#endif + +#ifdef PSI5_IP_ENABLE_INTERRUPTS_PSI5_0_CH2 +/** + * + * Function Name : Psi5_IRQ_Handle_PSI5_0_CH0 + * Description : Must be mapped to the generic interrupt of instace 0 channel 2. + */ +ISR(Psi5_IRQ_Handle_PSI5_0_CH2) +{ + Psi5_Ip_IRQ_Handler(PSI5_INSTANCE0, PSI5_0_CH2); +} +#endif + +#ifdef PSI5_IP_ENABLE_INTERRUPTS_PSI5_0_CH3 +/** + * + * Function Name : Psi5_IRQ_Handle_PSI5_0_CH0 + * Description : Must be mapped to the generic interrupt of instace 0 channel 3. + */ +ISR(Psi5_IRQ_Handle_PSI5_0_CH3) +{ + Psi5_Ip_IRQ_Handler(PSI5_INSTANCE0, PSI5_0_CH3); +} +#endif + +#ifdef PSI5_IP_ENABLE_INTERRUPTS_PSI5_1_CH0 +/** + * + * Function Name : Psi5_IRQ_Handle_PSI5_1_CH0 + * Description : Must be mapped to the generic interrupt of instace 1 channel 0. + */ +ISR(Psi5_IRQ_Handle_PSI5_1_CH0) +{ + Psi5_Ip_IRQ_Handler(PSI5_INSTANCE1, PSI5_1_CH0); +} +#endif + +#ifdef PSI5_IP_ENABLE_INTERRUPTS_PSI5_1_CH1 +/** + * + * Function Name : Psi5_IRQ_Handle_PSI5_1_CH0 + * Description : Must be mapped to the generic interrupt of instace 1 channel 1. + */ +ISR(Psi5_IRQ_Handle_PSI5_1_CH1) +{ + Psi5_Ip_IRQ_Handler(PSI5_INSTANCE1, PSI5_1_CH1); +} +#endif + +#ifdef PSI5_IP_ENABLE_INTERRUPTS_PSI5_1_CH2 +/** + * + * Function Name : Psi5_IRQ_Handle_PSI5_1_CH0 + * Description : Must be mapped to the generic interrupt of instace 1 channel 2. + */ +ISR(Psi5_IRQ_Handle_PSI5_1_CH2) +{ + Psi5_Ip_IRQ_Handler(PSI5_INSTANCE1, PSI5_1_CH2); +} +#endif + +#ifdef PSI5_IP_ENABLE_INTERRUPTS_PSI5_1_CH3 +/** + * + * Function Name : Psi5_IRQ_Handle_PSI5_0_CH0 + * Description : Must be mapped to the generic interrupt of instace 1 channel 3. + */ +ISR(Psi5_IRQ_Handle_PSI5_1_CH3) +{ + Psi5_Ip_IRQ_Handler(PSI5_INSTANCE1, PSI5_1_CH3); +} +#endif + +#define PSI5_STOP_SEC_CODE +#include "Psi5_MemMap.h" + +#ifdef __cplusplus +} +#endif + +/** @} */ diff --git a/s32/drivers/s32ze/Rte/CMakeLists.txt b/s32/drivers/s32ze/Rte/CMakeLists.txt index 754e2f461..3f2834f96 100644 --- a/s32/drivers/s32ze/Rte/CMakeLists.txt +++ b/s32/drivers/s32ze/Rte/CMakeLists.txt @@ -14,4 +14,5 @@ zephyr_library_sources_ifdef(CONFIG_NXP_S32_EMIOS src/SchM_Mcl.c) zephyr_library_sources_ifdef(CONFIG_PWM_NXP_S32_EMIOS src/SchM_Pwm.c) if(CONFIG_PWM_NXP_S32_EMIOS AND CONFIG_PWM_CAPTURE) zephyr_library_sources(src/SchM_Icu.c) -endif() \ No newline at end of file +endif() +zephyr_library_sources_ifdef(CONFIG_PSI5_NXP_S32 src/SchM_Psi5.c) diff --git a/s32/drivers/s32ze/Rte/include/SchM_Psi5.h b/s32/drivers/s32ze/Rte/include/SchM_Psi5.h new file mode 100644 index 000000000..ac1094a6d --- /dev/null +++ b/s32/drivers/s32ze/Rte/include/SchM_Psi5.h @@ -0,0 +1,123 @@ +/* + * Copyright 2021-2024 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/** +* @file SchM_Psi5.h +* @version 2.0.0 +* +* @brief AUTOSAR Rte - module interface +* @details This file contains the functions prototypes and data types of the AUTOSAR Rte. +* This file contains sample code only. It is not part of the production code deliverables. +* +* @addtogroup RTE_MODULE +* @{ +*/ + +#ifndef SCHM_PSI5_H +#define SCHM_PSI5_H + +#ifdef __cplusplus +extern "C" { +#endif +/*================================================================================================== +* INCLUDE FILES +* 1) system and project includes +* 2) needed interfaces from external units +* 3) internal and external interfaces from this unit +==================================================================================================*/ + +/*================================================================================================== +* SOURCE FILE VERSION INFORMATION +==================================================================================================*/ +#define SCHM_PSI5_AR_RELEASE_MAJOR_VERSION 4 +#define SCHM_PSI5_AR_RELEASE_MINOR_VERSION 7 +#define SCHM_PSI5_AR_RELEASE_REVISION_VERSION 0 +#define SCHM_PSI5_SW_MAJOR_VERSION 2 +#define SCHM_PSI5_SW_MINOR_VERSION 0 +#define SCHM_PSI5_SW_PATCH_VERSION 0 + +/*================================================================================================== +* FILE VERSION CHECKS +==================================================================================================*/ + + +/*================================================================================================== +* CONSTANTS +==================================================================================================*/ + +/*================================================================================================== +* DEFINES AND MACROS +==================================================================================================*/ +#define NUMBER_OF_CORES (uint8)(14U) + +/*================================================================================================== +* ENUMS +==================================================================================================*/ + +/*================================================================================================== +* STRUCTURES AND OTHER TYPEDEFS +==================================================================================================*/ + +/*================================================================================================== +* GLOBAL VARIABLE DECLARATIONS +==================================================================================================*/ + +/*================================================================================================== +* FUNCTION PROTOTYPES +==================================================================================================*/ +#define RTE_START_SEC_CODE +#include "Rte_MemMap.h" + +#ifdef MCAL_TESTING_ENVIRONMENT +/** +@brief This function checks that all entered exclusive areas were also exited. +@details This function checks that all entered exclusive areas were also exited. The check + is done by verifying that all reentry_guard_* static variables are back to the + zero value. + +@param[in] void No input parameters +@return void This function does not return a value. Test asserts are used instead. + +@pre None +@post None + +@remarks Covers +@remarks Implements +*/ +void SchM_Check_psi5(void); +#endif /*MCAL_TESTING_ENVIRONMENT*/ + +extern void SchM_Enter_Psi5_PSI5_EXCLUSIVE_AREA_00(void); +extern void SchM_Exit_Psi5_PSI5_EXCLUSIVE_AREA_00(void); + +extern void SchM_Enter_Psi5_PSI5_EXCLUSIVE_AREA_01(void); +extern void SchM_Exit_Psi5_PSI5_EXCLUSIVE_AREA_01(void); + +extern void SchM_Enter_Psi5_PSI5_EXCLUSIVE_AREA_02(void); +extern void SchM_Exit_Psi5_PSI5_EXCLUSIVE_AREA_02(void); + +extern void SchM_Enter_Psi5_PSI5_EXCLUSIVE_AREA_03(void); +extern void SchM_Exit_Psi5_PSI5_EXCLUSIVE_AREA_03(void); + +extern void SchM_Enter_Psi5_PSI5_EXCLUSIVE_AREA_04(void); +extern void SchM_Exit_Psi5_PSI5_EXCLUSIVE_AREA_04(void); + +extern void SchM_Enter_Psi5_PSI5_EXCLUSIVE_AREA_05(void); +extern void SchM_Exit_Psi5_PSI5_EXCLUSIVE_AREA_05(void); + + + + +#define RTE_STOP_SEC_CODE +#include "Rte_MemMap.h" + +#ifdef __cplusplus +} +#endif + +/** @} */ + +#endif /* SCHM_PSI5_H */ diff --git a/s32/drivers/s32ze/Rte/src/SchM_Psi5.c b/s32/drivers/s32ze/Rte/src/SchM_Psi5.c new file mode 100644 index 000000000..3e7a658e2 --- /dev/null +++ b/s32/drivers/s32ze/Rte/src/SchM_Psi5.c @@ -0,0 +1,654 @@ +/* + * Copyright 2021-2024 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/** +* @file SchM_Psi5.c +* @version 2.0.0 +* +* @brief AUTOSAR Rte - module implementation +* @details This module implements stubs for the AUTOSAR Rte +* This file contains sample code only. It is not part of the production code deliverables. +* +* @addtogroup RTE_MODULE +* @{ +*/ + +#ifdef __cplusplus +extern "C"{ +#endif + +/*================================================================================================== +* INCLUDE FILES +* 1) system and project includes +* 2) needed interfaces from external units +* 3) internal and external interfaces from this unit +==================================================================================================*/ +#include "Std_Types.h" +#include "Mcal.h" +#include "OsIf.h" +#include "SchM_Psi5.h" +#ifdef MCAL_TESTING_ENVIRONMENT +#include "EUnit.h" /* EUnit Test Suite */ +#endif + +/*================================================================================================== +* SOURCE FILE VERSION INFORMATION +==================================================================================================*/ +#define SCHM_PSI5_AR_RELEASE_MAJOR_VERSION_C 4 +#define SCHM_PSI5_AR_RELEASE_MINOR_VERSION_C 7 +#define SCHM_PSI5_AR_RELEASE_REVISION_VERSION_C 0 +#define SCHM_PSI5_SW_MAJOR_VERSION_C 2 +#define SCHM_PSI5_SW_MINOR_VERSION_C 0 +#define SCHM_PSI5_SW_PATCH_VERSION_C 0 + +/*================================================================================================== +* LOCAL CONSTANTS +==================================================================================================*/ +#ifdef MCAL_PLATFORM_ARM + #if (MCAL_PLATFORM_ARM == MCAL_ARM_AARCH64) + #define ISR_STATE_MASK ((uint32)0x000000C0UL) /**< @brief DAIF bit I and F */ + #elif (MCAL_PLATFORM_ARM == MCAL_ARM_RARCH) + #define ISR_STATE_MASK ((uint32)0x00000080UL) /**< @brief CPSR bit I */ + #else + #if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS)) + #define ISR_STATE_MASK ((uint32)0x000000FFUL) /**< @brief BASEPRI[7:0] mask */ + #else + #define ISR_STATE_MASK ((uint32)0x00000001UL) /**< @brief PRIMASK bit 0 */ + #endif + #endif +#else + #ifdef MCAL_PLATFORM_S12 + #define ISR_STATE_MASK ((uint32)0x00000010UL) /**< @brief I bit of CCR */ + #else + #define ISR_STATE_MASK ((uint32)0x00008000UL) /**< @brief EE bit of MSR */ + #endif +#endif +/*================================================================================================== +* LOCAL MACROS +==================================================================================================*/ +#ifdef MCAL_PLATFORM_ARM + #if (MCAL_PLATFORM_ARM == MCAL_ARM_AARCH64) + #define ISR_ON(msr) (uint32)(((uint32)(msr) & (uint32)(ISR_STATE_MASK)) != (uint32)(ISR_STATE_MASK)) + #elif (MCAL_PLATFORM_ARM == MCAL_ARM_RARCH) + #define ISR_ON(msr) (uint32)(((uint32)(msr) & (uint32)(ISR_STATE_MASK)) != (uint32)(ISR_STATE_MASK)) + #else + #define ISR_ON(msr) (uint32)(((uint32)(msr) & (uint32)(ISR_STATE_MASK)) == (uint32)0) + #endif +#else + #ifdef MCAL_PLATFORM_S12 + #define ISR_ON(msr) (uint32)(((uint32)(msr) & (uint32)(ISR_STATE_MASK)) == (uint32)0) + #else + #define ISR_ON(msr) (uint32)((uint32)(msr) & (uint32)(ISR_STATE_MASK)) + #endif +#endif + +/*================================================================================================== +* FILE VERSION CHECKS +==================================================================================================*/ + +/*================================================================================================== +* LOCAL TYPEDEFS (STRUCTURES, UNIONS, ENUMS) +==================================================================================================*/ + + +/*================================================================================================== +* LOCAL VARIABLES +==================================================================================================*/ +#define RTE_START_SEC_VAR_CLEARED_32_NO_CACHEABLE +#include "Rte_MemMap.h" +VAR_SEC_NOCACHE(msr_PSI5_EXCLUSIVE_AREA_00) static volatile uint32 msr_PSI5_EXCLUSIVE_AREA_00[NUMBER_OF_CORES]; +VAR_SEC_NOCACHE(reentry_guard_PSI5_EXCLUSIVE_AREA_00) static volatile uint32 reentry_guard_PSI5_EXCLUSIVE_AREA_00[NUMBER_OF_CORES]; +VAR_SEC_NOCACHE(msr_PSI5_EXCLUSIVE_AREA_01) static volatile uint32 msr_PSI5_EXCLUSIVE_AREA_01[NUMBER_OF_CORES]; +VAR_SEC_NOCACHE(reentry_guard_PSI5_EXCLUSIVE_AREA_01) static volatile uint32 reentry_guard_PSI5_EXCLUSIVE_AREA_01[NUMBER_OF_CORES]; +VAR_SEC_NOCACHE(msr_PSI5_EXCLUSIVE_AREA_02) static volatile uint32 msr_PSI5_EXCLUSIVE_AREA_02[NUMBER_OF_CORES]; +VAR_SEC_NOCACHE(reentry_guard_PSI5_EXCLUSIVE_AREA_02) static volatile uint32 reentry_guard_PSI5_EXCLUSIVE_AREA_02[NUMBER_OF_CORES]; +VAR_SEC_NOCACHE(msr_PSI5_EXCLUSIVE_AREA_03) static volatile uint32 msr_PSI5_EXCLUSIVE_AREA_03[NUMBER_OF_CORES]; +VAR_SEC_NOCACHE(reentry_guard_PSI5_EXCLUSIVE_AREA_03) static volatile uint32 reentry_guard_PSI5_EXCLUSIVE_AREA_03[NUMBER_OF_CORES]; +VAR_SEC_NOCACHE(msr_PSI5_EXCLUSIVE_AREA_04) static volatile uint32 msr_PSI5_EXCLUSIVE_AREA_04[NUMBER_OF_CORES]; +VAR_SEC_NOCACHE(reentry_guard_PSI5_EXCLUSIVE_AREA_04) static volatile uint32 reentry_guard_PSI5_EXCLUSIVE_AREA_04[NUMBER_OF_CORES]; +VAR_SEC_NOCACHE(msr_PSI5_EXCLUSIVE_AREA_05) static volatile uint32 msr_PSI5_EXCLUSIVE_AREA_05[NUMBER_OF_CORES]; +VAR_SEC_NOCACHE(reentry_guard_PSI5_EXCLUSIVE_AREA_05) static volatile uint32 reentry_guard_PSI5_EXCLUSIVE_AREA_05[NUMBER_OF_CORES]; + +#define RTE_STOP_SEC_VAR_CLEARED_32_NO_CACHEABLE +#include "Rte_MemMap.h" +/*================================================================================================== +* GLOBAL CONSTANTS +==================================================================================================*/ + + +/*================================================================================================== +* GLOBAL VARIABLES +==================================================================================================*/ + +/*================================================================================================== +* LOCAL FUNCTION PROTOTYPES +==================================================================================================*/ + +#ifndef _COSMIC_C_S32ZE_ +/*================================================================================================*/ +/** +* @brief This function returns the MSR register value (32 bits). +* @details This function returns the MSR register value (32 bits). +* +* @param[in] void No input parameters +* @return uint32 msr This function returns the MSR register value (32 bits). +* +* @pre None +* @post None +* +*/ +uint32 Psi5_schm_read_msr(void); +#endif /*ifndef _COSMIC_C_S32ZE_*/ +/*================================================================================================== +* LOCAL FUNCTIONS +==================================================================================================*/ +#define RTE_START_SEC_CODE +#include "Rte_MemMap.h" + +#if (defined(_GREENHILLS_C_S32ZE_) || defined(_CODEWARRIOR_C_S32ZE_)) +/*================================================================================================*/ +/** +* @brief This macro returns the MSR register value (32 bits). +* @details This macro function implementation returns the MSR register value in r3 (32 bits). +* +* @pre None +* @post None +* +*/ +#ifdef MCAL_PLATFORM_ARM +#if (MCAL_PLATFORM_ARM == MCAL_ARM_AARCH64) +ASM_KEYWORD uint32 Psi5_schm_read_msr(void) +{ + mrs x0, S3_3_c4_c2_1 +} +#elif (MCAL_PLATFORM_ARM == MCAL_ARM_RARCH) +ASM_KEYWORD uint32 Psi5_schm_read_msr(void) +{ + mrs r0, CPSR +} +#else +ASM_KEYWORD uint32 Psi5_schm_read_msr(void) +{ +#if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS)) + mrs r0, BASEPRI +#else + mrs r0, PRIMASK +#endif +} +#endif +#else +#ifdef MCAL_PLATFORM_S12 +ASM_KEYWORD uint32 Psi5_schm_read_msr(void) +{ + tfr ccr, d6 +} +#else +ASM_KEYWORD uint32 Psi5_schm_read_msr(void) +{ + mfmsr r3 +} +#endif +#endif +#endif /*#ifdef GHS||CW*/ + +#ifdef _DIABDATA_C_S32ZE_ +/** +* @brief This function returns the MSR register value (32 bits). +* @details This function returns the MSR register value (32 bits). +* +* @param[in] void No input parameters +* @return uint32 msr This function returns the MSR register value (32 bits). +* +* @pre None +* @post None +* +*/ +#ifdef MCAL_PLATFORM_ARM +uint32 Psi5_schm_read_msr(void) +{ + register uint32 reg_tmp; + #if (MCAL_PLATFORM_ARM == MCAL_ARM_AARCH64) + __asm volatile( " mrs %x0, DAIF " : "=r" (reg_tmp) ); + #elif (MCAL_PLATFORM_ARM == MCAL_ARM_RARCH) + __asm volatile( " mrs %0, CPSR " : "=r" (reg_tmp) ); + #else + #if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS)) + __asm volatile( " mrs %0, basepri " : "=r" (reg_tmp) ); + #else + __asm volatile( " mrs %0, primask " : "=r" (reg_tmp) ); + #endif + #endif + return (uint32)reg_tmp; +} +#else +ASM_KEYWORD uint32 Psi5_schm_read_msr(void) +{ + mfmsr r3 +} +#endif /* MCAL_PLATFORM_ARM */ + +#endif /* _DIABDATA_C_S32ZE_*/ + +#ifdef _COSMIC_C_S32ZE_ +/*================================================================================================*/ +/** +* @brief This function returns the MSR register value (32 bits). +* @details This function returns the MSR register value (32 bits). +* +* @param[in] void No input parameters +* @return uint32 msr This function returns the MSR register value (32 bits). +* +* @pre None +* @post None +* +*/ + +#ifdef MCAL_PLATFORM_S12 + #define Psi5_schm_read_msr() ASM_KEYWORD("tfr ccr, d6") +#else + #define Psi5_schm_read_msr() ASM_KEYWORD("mfmsr r3") +#endif + +#endif /*Cosmic compiler only*/ + + +#ifdef _HITECH_C_S32ZE_ +/*================================================================================================*/ +/** +* @brief This function returns the MSR register value (32 bits). +* @details This function returns the MSR register value (32 bits). +* +* @param[in] void No input parameters +* @return uint32 msr This function returns the MSR register value (32 bits). +* +* @pre None +* @post None +* +*/ +uint32 Psi5_schm_read_msr(void) +{ + uint32 result; + __asm volatile("mfmsr %0" : "=r" (result) :); + return result; +} + +#endif /*HighTec compiler only*/ + /*================================================================================================*/ +#ifdef _GCC_C_S32ZE_ +/** +* @brief This function returns the MSR register value (32 bits). +* @details This function returns the MSR register value (32 bits). +* +* @param[in] void No input parameters +* @return uint32 msr This function returns the MSR register value (32 bits). +* +* @pre None +* @post None +* +*/ +uint32 Psi5_schm_read_msr(void) +{ + register uint32 reg_tmp; + #if (MCAL_PLATFORM_ARM == MCAL_ARM_AARCH64) + __asm volatile( " mrs %x0, DAIF " : "=r" (reg_tmp) ); + #elif (MCAL_PLATFORM_ARM == MCAL_ARM_RARCH) + __asm volatile( " mrs %0, CPSR " : "=r" (reg_tmp) ); + #else + #if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS)) + __asm volatile( " mrs %0, basepri " : "=r" (reg_tmp) ); + #else + __asm volatile( " mrs %0, primask " : "=r" (reg_tmp) ); + #endif + #endif + return (uint32)reg_tmp; +} +#endif /* _GCC_C_S32ZE_*/ +/*================================================================================================*/ + +#ifdef _ARM_DS5_C_S32ZE_ +/** +* @brief This function returns the MSR register value (32 bits). +* @details This function returns the MSR register value (32 bits). +* +* @param[in] void No input parameters +* @return uint32 msr This function returns the MSR register value (32 bits). +* +* @pre None +* @post None +* +*/ +uint32 Psi5_schm_read_msr(void) +{ + register uint32 reg_tmp; + #if (MCAL_PLATFORM_ARM == MCAL_ARM_AARCH64) + __asm volatile( " mrs %x0, DAIF " : "=r" (reg_tmp) ); + #elif (MCAL_PLATFORM_ARM == MCAL_ARM_RARCH) + __asm volatile( " mrs %0, CPSR " : "=r" (reg_tmp) ); + #else + #if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS)) + __asm volatile( " mrs %0, basepri " : "=r" (reg_tmp) ); + #else + __asm volatile( " mrs %0, primask " : "=r" (reg_tmp) ); + #endif + #endif + return (uint32)reg_tmp; +} +#endif /* _ARM_DS5_C_S32ZE_ */ + +#ifdef _IAR_C_S32ZE_ +/** +* @brief This function returns the MSR register value (32 bits). +* @details This function returns the MSR register value (32 bits). +* +* @param[in] void No input parameters +* @return uint32 msr This function returns the MSR register value (32 bits). +* +* @pre None +* @post None +* +*/ +uint32 Psi5_schm_read_msr(void) +{ + register uint32 reg_tmp; + +#if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS)) + __asm volatile( " mrs %0, basepri " : "=r" (reg_tmp) ); +#else + __asm volatile( " mrs %0, primask " : "=r" (reg_tmp) ); +#endif + + return (uint32)reg_tmp; +} +#endif /* _IAR_C_S32ZE_ */ + +#define RTE_STOP_SEC_CODE +#include "Rte_MemMap.h" + +/*================================================================================================== +* GLOBAL FUNCTIONS +==================================================================================================*/ +#define RTE_START_SEC_CODE +#include "Rte_MemMap.h" + +void SchM_Enter_Psi5_PSI5_EXCLUSIVE_AREA_00(void) +{ + uint32 msr; + uint32 u32CoreId = (uint32)OsIf_GetCoreID(); + + if(0UL == reentry_guard_PSI5_EXCLUSIVE_AREA_00[u32CoreId]) + { +#if (defined MCAL_ENABLE_USER_MODE_SUPPORT) + msr = OsIf_Trusted_Call_Return(Psi5_schm_read_msr); +#else + msr = Psi5_schm_read_msr(); /*read MSR (to store interrupts state)*/ +#endif /* MCAL_ENABLE_USER_MODE_SUPPORT */ + if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/ + { + OsIf_SuspendAllInterrupts(); +#ifdef _ARM_DS5_C_S32ZE_ + ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/ +#endif + } + msr_PSI5_EXCLUSIVE_AREA_00[u32CoreId] = msr; + } + reentry_guard_PSI5_EXCLUSIVE_AREA_00[u32CoreId]++; +} + +void SchM_Exit_Psi5_PSI5_EXCLUSIVE_AREA_00(void) +{ + uint32 u32CoreId = (uint32)OsIf_GetCoreID(); + + reentry_guard_PSI5_EXCLUSIVE_AREA_00[u32CoreId]--; + if ((ISR_ON(msr_PSI5_EXCLUSIVE_AREA_00[u32CoreId]))&&(0UL == reentry_guard_PSI5_EXCLUSIVE_AREA_00[u32CoreId])) /*if interrupts were enabled*/ + { + OsIf_ResumeAllInterrupts(); +#ifdef _ARM_DS5_C_S32ZE_ + ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/ +#endif + } +} + +void SchM_Enter_Psi5_PSI5_EXCLUSIVE_AREA_01(void) +{ + uint32 msr; + uint32 u32CoreId = (uint32)OsIf_GetCoreID(); + + if(0UL == reentry_guard_PSI5_EXCLUSIVE_AREA_01[u32CoreId]) + { +#if (defined MCAL_ENABLE_USER_MODE_SUPPORT) + msr = OsIf_Trusted_Call_Return(Psi5_schm_read_msr); +#else + msr = Psi5_schm_read_msr(); /*read MSR (to store interrupts state)*/ +#endif /* MCAL_ENABLE_USER_MODE_SUPPORT */ + if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/ + { + OsIf_SuspendAllInterrupts(); +#ifdef _ARM_DS5_C_S32ZE_ + ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/ +#endif + } + msr_PSI5_EXCLUSIVE_AREA_01[u32CoreId] = msr; + } + reentry_guard_PSI5_EXCLUSIVE_AREA_01[u32CoreId]++; +} + +void SchM_Exit_Psi5_PSI5_EXCLUSIVE_AREA_01(void) +{ + uint32 u32CoreId = (uint32)OsIf_GetCoreID(); + + reentry_guard_PSI5_EXCLUSIVE_AREA_01[u32CoreId]--; + if ((ISR_ON(msr_PSI5_EXCLUSIVE_AREA_01[u32CoreId]))&&(0UL == reentry_guard_PSI5_EXCLUSIVE_AREA_01[u32CoreId])) /*if interrupts were enabled*/ + { + OsIf_ResumeAllInterrupts(); +#ifdef _ARM_DS5_C_S32ZE_ + ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/ +#endif + } +} + +void SchM_Enter_Psi5_PSI5_EXCLUSIVE_AREA_02(void) +{ + uint32 msr; + uint32 u32CoreId = (uint32)OsIf_GetCoreID(); + + if(0UL == reentry_guard_PSI5_EXCLUSIVE_AREA_02[u32CoreId]) + { +#if (defined MCAL_ENABLE_USER_MODE_SUPPORT) + msr = OsIf_Trusted_Call_Return(Psi5_schm_read_msr); +#else + msr = Psi5_schm_read_msr(); /*read MSR (to store interrupts state)*/ +#endif /* MCAL_ENABLE_USER_MODE_SUPPORT */ + if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/ + { + OsIf_SuspendAllInterrupts(); +#ifdef _ARM_DS5_C_S32ZE_ + ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/ +#endif + } + msr_PSI5_EXCLUSIVE_AREA_02[u32CoreId] = msr; + } + reentry_guard_PSI5_EXCLUSIVE_AREA_02[u32CoreId]++; +} + +void SchM_Exit_Psi5_PSI5_EXCLUSIVE_AREA_02(void) +{ + uint32 u32CoreId = (uint32)OsIf_GetCoreID(); + + reentry_guard_PSI5_EXCLUSIVE_AREA_02[u32CoreId]--; + if ((ISR_ON(msr_PSI5_EXCLUSIVE_AREA_02[u32CoreId]))&&(0UL == reentry_guard_PSI5_EXCLUSIVE_AREA_02[u32CoreId])) /*if interrupts were enabled*/ + { + OsIf_ResumeAllInterrupts(); +#ifdef _ARM_DS5_C_S32ZE_ + ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/ +#endif + } +} + +void SchM_Enter_Psi5_PSI5_EXCLUSIVE_AREA_03(void) +{ + uint32 msr; + uint32 u32CoreId = (uint32)OsIf_GetCoreID(); + + if(0UL == reentry_guard_PSI5_EXCLUSIVE_AREA_03[u32CoreId]) + { +#if (defined MCAL_ENABLE_USER_MODE_SUPPORT) + msr = OsIf_Trusted_Call_Return(Psi5_schm_read_msr); +#else + msr = Psi5_schm_read_msr(); /*read MSR (to store interrupts state)*/ +#endif /* MCAL_ENABLE_USER_MODE_SUPPORT */ + if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/ + { + OsIf_SuspendAllInterrupts(); +#ifdef _ARM_DS5_C_S32ZE_ + ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/ +#endif + } + msr_PSI5_EXCLUSIVE_AREA_03[u32CoreId] = msr; + } + reentry_guard_PSI5_EXCLUSIVE_AREA_03[u32CoreId]++; +} + +void SchM_Exit_Psi5_PSI5_EXCLUSIVE_AREA_03(void) +{ + uint32 u32CoreId = (uint32)OsIf_GetCoreID(); + + reentry_guard_PSI5_EXCLUSIVE_AREA_03[u32CoreId]--; + if ((ISR_ON(msr_PSI5_EXCLUSIVE_AREA_03[u32CoreId]))&&(0UL == reentry_guard_PSI5_EXCLUSIVE_AREA_03[u32CoreId])) /*if interrupts were enabled*/ + { + OsIf_ResumeAllInterrupts(); +#ifdef _ARM_DS5_C_S32ZE_ + ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/ +#endif + } +} + +void SchM_Enter_Psi5_PSI5_EXCLUSIVE_AREA_04(void) +{ + uint32 msr; + uint32 u32CoreId = (uint32)OsIf_GetCoreID(); + + if(0UL == reentry_guard_PSI5_EXCLUSIVE_AREA_04[u32CoreId]) + { +#if (defined MCAL_ENABLE_USER_MODE_SUPPORT) + msr = OsIf_Trusted_Call_Return(Psi5_schm_read_msr); +#else + msr = Psi5_schm_read_msr(); /*read MSR (to store interrupts state)*/ +#endif /* MCAL_ENABLE_USER_MODE_SUPPORT */ + if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/ + { + OsIf_SuspendAllInterrupts(); +#ifdef _ARM_DS5_C_S32ZE_ + ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/ +#endif + } + msr_PSI5_EXCLUSIVE_AREA_04[u32CoreId] = msr; + } + reentry_guard_PSI5_EXCLUSIVE_AREA_04[u32CoreId]++; +} + +void SchM_Exit_Psi5_PSI5_EXCLUSIVE_AREA_04(void) +{ + uint32 u32CoreId = (uint32)OsIf_GetCoreID(); + + reentry_guard_PSI5_EXCLUSIVE_AREA_04[u32CoreId]--; + if ((ISR_ON(msr_PSI5_EXCLUSIVE_AREA_04[u32CoreId]))&&(0UL == reentry_guard_PSI5_EXCLUSIVE_AREA_04[u32CoreId])) /*if interrupts were enabled*/ + { + OsIf_ResumeAllInterrupts(); +#ifdef _ARM_DS5_C_S32ZE_ + ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/ +#endif + } +} + +void SchM_Enter_Psi5_PSI5_EXCLUSIVE_AREA_05(void) +{ + uint32 msr; + uint32 u32CoreId = (uint32)OsIf_GetCoreID(); + + if(0UL == reentry_guard_PSI5_EXCLUSIVE_AREA_05[u32CoreId]) + { +#if (defined MCAL_ENABLE_USER_MODE_SUPPORT) + msr = OsIf_Trusted_Call_Return(Psi5_schm_read_msr); +#else + msr = Psi5_schm_read_msr(); /*read MSR (to store interrupts state)*/ +#endif /* MCAL_ENABLE_USER_MODE_SUPPORT */ + if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/ + { + OsIf_SuspendAllInterrupts(); +#ifdef _ARM_DS5_C_S32ZE_ + ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/ +#endif + } + msr_PSI5_EXCLUSIVE_AREA_05[u32CoreId] = msr; + } + reentry_guard_PSI5_EXCLUSIVE_AREA_05[u32CoreId]++; +} + +void SchM_Exit_Psi5_PSI5_EXCLUSIVE_AREA_05(void) +{ + uint32 u32CoreId = (uint32)OsIf_GetCoreID(); + + reentry_guard_PSI5_EXCLUSIVE_AREA_05[u32CoreId]--; + if ((ISR_ON(msr_PSI5_EXCLUSIVE_AREA_05[u32CoreId]))&&(0UL == reentry_guard_PSI5_EXCLUSIVE_AREA_05[u32CoreId])) /*if interrupts were enabled*/ + { + OsIf_ResumeAllInterrupts(); +#ifdef _ARM_DS5_C_S32ZE_ + ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/ +#endif + } +} + + +#ifdef MCAL_TESTING_ENVIRONMENT +/** +@brief This function checks that all entered exclusive areas were also exited. +@details This function checks that all entered exclusive areas were also exited. The check + is done by verifying that all reentry_guard_* static variables are back to the + zero value. + +@param[in] void No input parameters +@return void This function does not return a value. Test asserts are used instead. + +@pre None +@post None + +@remarks Covers +@remarks Implements +*/ +void SchM_Check_psi5(void) +{ + uint32 u32CoreId = (uint32)OsIf_GetCoreID(); + + EU_ASSERT(0UL == reentry_guard_PSI5_EXCLUSIVE_AREA_00[u32CoreId]); + reentry_guard_PSI5_EXCLUSIVE_AREA_00[u32CoreId] = 0UL; /*reset reentry_guard_PSI5_EXCLUSIVE_AREA_00 for the next test in the suite*/ + + EU_ASSERT(0UL == reentry_guard_PSI5_EXCLUSIVE_AREA_01[u32CoreId]); + reentry_guard_PSI5_EXCLUSIVE_AREA_01[u32CoreId] = 0UL; /*reset reentry_guard_PSI5_EXCLUSIVE_AREA_01 for the next test in the suite*/ + + EU_ASSERT(0UL == reentry_guard_PSI5_EXCLUSIVE_AREA_02[u32CoreId]); + reentry_guard_PSI5_EXCLUSIVE_AREA_02[u32CoreId] = 0UL; /*reset reentry_guard_PSI5_EXCLUSIVE_AREA_02 for the next test in the suite*/ + + EU_ASSERT(0UL == reentry_guard_PSI5_EXCLUSIVE_AREA_03[u32CoreId]); + reentry_guard_PSI5_EXCLUSIVE_AREA_03[u32CoreId] = 0UL; /*reset reentry_guard_PSI5_EXCLUSIVE_AREA_03 for the next test in the suite*/ + + EU_ASSERT(0UL == reentry_guard_PSI5_EXCLUSIVE_AREA_04[u32CoreId]); + reentry_guard_PSI5_EXCLUSIVE_AREA_04[u32CoreId] = 0UL; /*reset reentry_guard_PSI5_EXCLUSIVE_AREA_04 for the next test in the suite*/ + + EU_ASSERT(0UL == reentry_guard_PSI5_EXCLUSIVE_AREA_05[u32CoreId]); + reentry_guard_PSI5_EXCLUSIVE_AREA_05[u32CoreId] = 0UL; /*reset reentry_guard_PSI5_EXCLUSIVE_AREA_05 for the next test in the suite*/ + + +} +#endif /*MCAL_TESTING_ENVIRONMENT*/ + +#define RTE_STOP_SEC_CODE +#include "Rte_MemMap.h" + +#ifdef __cplusplus +} +#endif + +/** @} */ diff --git a/s32/soc/s32z270/include/Psi5_Ip_Cfg.h b/s32/soc/s32z270/include/Psi5_Ip_Cfg.h new file mode 100644 index 000000000..657c71e37 --- /dev/null +++ b/s32/soc/s32z270/include/Psi5_Ip_Cfg.h @@ -0,0 +1,193 @@ +/* + * Copyright 2021-2024 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef PSI5_IP_CFG_H +#define PSI5_IP_CFG_H + +/** +* @file Psi5_Ip_Cfg.h +* +* @addtogroup PSI5_IP PSI5 IPV Driver +* @{ +*/ + +#ifdef __cplusplus +extern "C"{ +#endif +/*================================================================================================== +* INCLUDE FILES +* 1) system and project includes +* 2) needed interfaces from external units +* 3) internal and external interfaces from this unit +==================================================================================================*/ +#include "Mcal.h" + +#include "Psi5_Ip_Init_PBcfg.h" + +#include "Psi5_Ip_Types.h" +#include "Psi5_Ip_Cfg_Defines.h" +#if (STD_ON == PSI5_IP_DMA_IS_USED) +#include "CDD_Mcl.h" +#endif +/*================================================================================================== +* SOURCE FILE VERSION INFORMATION +==================================================================================================*/ +#define PSI5_IP_CFG_VENDOR_ID 43 +#define PSI5_IP_CFG_AR_RELEASE_MAJOR_VERSION 4 +#define PSI5_IP_CFG_AR_RELEASE_MINOR_VERSION 7 +#define PSI5_IP_CFG_AR_RELEASE_REVISION_VERSION 0 +#define PSI5_IP_CFG_SW_MAJOR_VERSION 2 +#define PSI5_IP_CFG_SW_MINOR_VERSION 0 +#define PSI5_IP_CFG_SW_PATCH_VERSION 0 + +/*================================================================================================== +* FILE VERSION CHECKS +==================================================================================================*/ +/* Check if Psi5_Ip_Cfg.h and Psi5_Ip_Init_PBcfg.h header file are of the same vendor */ +#if (PSI5_IP_CFG_VENDOR_ID != PSI5_IP_INIT_PBCFG_VENDOR_ID) + #error "Psi5_Ip_Cfg.h and Psi5_Ip_Init_PBcfg.h have different vendor ids" +#endif +/* Check if Psi5_Ip_Cfg.h and Psi5_Ip_Init_PBcfg.h header file are of the same Autosar version */ +#if ((PSI5_IP_CFG_AR_RELEASE_MAJOR_VERSION != PSI5_IP_INIT_PBCFG_AR_RELEASE_MAJOR_VERSION) || \ + (PSI5_IP_CFG_AR_RELEASE_MINOR_VERSION != PSI5_IP_INIT_PBCFG_AR_RELEASE_MINOR_VERSION) || \ + (PSI5_IP_CFG_AR_RELEASE_REVISION_VERSION != PSI5_IP_INIT_PBCFG_AR_RELEASE_REVISION_VERSION)) + #error "AUTOSAR Version Numbers of Psi5_Ip_Cfg.h and Psi5_Ip_Init_PBcfg.h are different" +#endif +/* Check if Psi5_Ip_Cfg.h and Psi5_Ip_Init_PBcfg.h header file are of the same software version */ +#if ((PSI5_IP_CFG_SW_MAJOR_VERSION != PSI5_IP_INIT_PBCFG_SW_MAJOR_VERSION) || \ + (PSI5_IP_CFG_SW_MINOR_VERSION != PSI5_IP_INIT_PBCFG_SW_MINOR_VERSION) || \ + (PSI5_IP_CFG_SW_PATCH_VERSION != PSI5_IP_INIT_PBCFG_SW_PATCH_VERSION)) + #error "Software Version Numbers of Psi5_Ip_Cfg.h and Psi5_Ip_Init_PBcfg.h are different" +#endif + +/* Checks against Psi5_Ip_Types.h */ +#if (PSI5_IP_CFG_VENDOR_ID != PSI5_IP_TYPES_VENDOR_ID) + #error "Psi5_Ip_Cfg.h and Psi5_Ip_Types.h have different vendor ids" +#endif +#if ((PSI5_IP_CFG_AR_RELEASE_MAJOR_VERSION != PSI5_IP_TYPES_AR_RELEASE_MAJOR_VERSION) || \ + (PSI5_IP_CFG_AR_RELEASE_MINOR_VERSION != PSI5_IP_TYPES_AR_RELEASE_MINOR_VERSION) || \ + (PSI5_IP_CFG_AR_RELEASE_REVISION_VERSION != PSI5_IP_TYPES_AR_RELEASE_REVISION_VERSION)) + #error "AUTOSAR Version Numbers of Psi5_Ip.h and Psi5_Ip_Types.h are different" +#endif +#if ((PSI5_IP_CFG_SW_MAJOR_VERSION != PSI5_IP_TYPES_SW_MAJOR_VERSION) || \ + (PSI5_IP_CFG_SW_MINOR_VERSION != PSI5_IP_TYPES_SW_MINOR_VERSION) || \ + (PSI5_IP_CFG_SW_PATCH_VERSION != PSI5_IP_TYPES_SW_PATCH_VERSION)) + #error "Software Version Numbers of Psi5_Ip_Cfg.h and Psi5_Ip_Types.h are different" +#endif + +/* Checks against Psi5_Ip_Cfg_Defines.h */ +#if (PSI5_IP_CFG_VENDOR_ID != PSI5_IP_CFG_DEFINES_VENDOR_ID) + #error "Psi5_Ip_Cfg.h and Psi5_Ip_Cfg_Defines.h have different vendor ids" +#endif +#if ((PSI5_IP_CFG_AR_RELEASE_MAJOR_VERSION != PSI5_IP_CFG_DEFINES_AR_RELEASE_MAJOR_VERSION) || \ + (PSI5_IP_CFG_AR_RELEASE_MINOR_VERSION != PSI5_IP_CFG_DEFINES_AR_RELEASE_MINOR_VERSION) || \ + (PSI5_IP_CFG_AR_RELEASE_REVISION_VERSION != PSI5_IP_CFG_DEFINES_AR_RELEASE_REVISION_VERSION)) + #error "AUTOSAR Version Numbers of Psi5_Ip_Cfg.h and Psi5_Ip_Cfg_Defines.h are different" +#endif +#if ((PSI5_IP_CFG_SW_MAJOR_VERSION != PSI5_IP_CFG_DEFINES_SW_MAJOR_VERSION) || \ + (PSI5_IP_CFG_SW_MINOR_VERSION != PSI5_IP_CFG_DEFINES_SW_MINOR_VERSION) || \ + (PSI5_IP_CFG_SW_PATCH_VERSION != PSI5_IP_CFG_DEFINES_SW_PATCH_VERSION)) + #error "Software Version Numbers of Psi5_Ip_Cfg.h and Psi5_Ip_Cfg_Defines.h are different" +#endif + +#if (STD_ON == PSI5_IP_DMA_IS_USED) +/* Check Psi5_Ip_Cfg.h against CDD_Mcl.h file versions */ +#ifndef DISABLE_MCAL_INTERMODULE_ASR_CHECK + #if ((PSI5_IP_CFG_AR_RELEASE_MAJOR_VERSION != CDD_MCL_AR_RELEASE_MAJOR_VERSION) || \ + (PSI5_IP_CFG_AR_RELEASE_MINOR_VERSION != CDD_MCL_AR_RELEASE_MINOR_VERSION)) + #error "AutoSar Version Numbers of Psi5_Ip_Cfg.h and CDD_Mcl.h are different" + #endif +#endif +#endif + +/*================================================================================================== +* DEFINES AND MACROS +==================================================================================================*/ +/** +* @brief Collection of all configuration structures declarations. +*/ +#define PSI5_IP_CONFIG_EXT +/** +* @brief Switches the Psi5_Ip_Transmit() API ON or OFF. +* +* @api +* +*/ +#define PSI5_IP_TRANSMIT_API (STD_ON) + +/** +* @brief Switches the Psi5_Ip_GetTransmissionStatus() API ON or OFF. +* +* @api +* +*/ +#define PSI5_IP_GET_TRANSMISSION_STATUS_API (STD_ON) + +/** +* @brief Switches the Psi5_Ip_GetPsi5Frame() API ON or OFF. +* +* @api +* +*/ +#define PSI5_IP_GET_PSI5_FRAME_API (STD_ON) + +/** +* @brief Switches the Psi5_Ip_GetSmcFrame() API ON or OFF. +* +* @api +* +*/ +#define PSI5_IP_GET_SMC_FRAME_API (STD_ON) + +/** +* @brief Switches the Psi5_Ip_SetGlobalSync() API ON or OFF. +* +* @api +* +*/ +#define PSI5_IP_SET_GLOBAL_SYNC_API (STD_ON) + +/** +* @brief Switches the Psi5_Ip_SetChannelSync() API ON or OFF. +* +* @api +* +*/ +#define PSI5_IP_SET_CHANNEL_SYNC_API (STD_ON) + +/*================================================================================================== +* ENUMS +==================================================================================================*/ + +/*================================================================================================== +* STRUCTURES AND OTHER TYPEDEFS +==================================================================================================*/ + +/*================================================================================================== +* GLOBAL VARIABLE DECLARATIONS +==================================================================================================*/ + +/*================================================================================================== +* GLOBAL CONSTANTS +==================================================================================================*/ + +/*================================================================================================== +* FUNCTION PROTOTYPES +==================================================================================================*/ +#define PSI5_START_SEC_CODE +#include "Psi5_MemMap.h" + +#define PSI5_STOP_SEC_CODE +#include "Psi5_MemMap.h" + +#ifdef __cplusplus +} +#endif + +/** @} */ + +#endif /* PSI5_IP_CFG_H */ + diff --git a/s32/soc/s32z270/include/Psi5_Ip_Cfg_Defines.h b/s32/soc/s32z270/include/Psi5_Ip_Cfg_Defines.h new file mode 100644 index 000000000..5cd597c44 --- /dev/null +++ b/s32/soc/s32z270/include/Psi5_Ip_Cfg_Defines.h @@ -0,0 +1,85 @@ +/* + * Copyright 2021-2024 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef PSI5_IP_CFG_DEFINES_H +#define PSI5_IP_CFG_DEFINES_H + +/** +* @file Psi5_Ip_Cfg_Defines.h +* +* @addtogroup PSI5_IP PSI5 IPV Driver +* @{ +*/ + + +#ifdef __cplusplus +extern "C"{ +#endif +/*================================================================================================== +* INCLUDE FILES +* 1) system and project includes +* 2) needed interfaces from external units +* 3) internal and external interfaces from this unit +==================================================================================================*/ +#include "S32Z2_PSI5.h" +/*================================================================================================== +* SOURCE FILE VERSION INFORMATION +==================================================================================================*/ +#define PSI5_IP_CFG_DEFINES_VENDOR_ID 43 +#define PSI5_IP_CFG_DEFINES_AR_RELEASE_MAJOR_VERSION 4 +#define PSI5_IP_CFG_DEFINES_AR_RELEASE_MINOR_VERSION 7 +#define PSI5_IP_CFG_DEFINES_AR_RELEASE_REVISION_VERSION 0 +#define PSI5_IP_CFG_DEFINES_SW_MAJOR_VERSION 2 +#define PSI5_IP_CFG_DEFINES_SW_MINOR_VERSION 0 +#define PSI5_IP_CFG_DEFINES_SW_PATCH_VERSION 0 +/*================================================================================================== +* FILE VERSION CHECKS +==================================================================================================*/ + +/*================================================================================================== +* GLOBAL VARIABLE DECLARATIONS +==================================================================================================*/ + +/*================================================================================================== +* ENUMS +==================================================================================================*/ + +/*================================================================================================== +* CONSTANTS +==================================================================================================*/ + +/*================================================================================================== +* DEFINES AND MACROS +==================================================================================================*/ +/* @brief Enables / Disables multipartition support */ +#define PSI5_IP_MULTIPARTITION_SUPPORT (STD_ON) + +#define PSI5_IP_DEV_ERROR_DETECT (STD_OFF) + +/* Define for HW channelId of channel Psi5Channel_0 */ +#define PSI5_0_CH0 (0U) +#define PSI5_IP_ENABLE_INTERRUPTS_PSI5_0_CH0 + + +#define PSI5_IP_DMA_IS_USED (STD_OFF) +#define PSI5_IP_DMA_PSI5_FRAME_IS_USED (STD_OFF) +#define PSI5_IP_DMA_SMC_FRAME_IS_USED (STD_OFF) + +/*================================================================================================== +* STRUCTURES AND OTHER TYPEDEFS +==================================================================================================*/ + +/*================================================================================================== +* FUNCTION PROTOTYPES +==================================================================================================*/ +#ifdef __cplusplus +} +#endif + +/** @} */ + +#endif /* PSI5_IP_CFG_DEFINES_H */ + diff --git a/s32/soc/s32z270/include/Psi5_Ip_Init_PBcfg.h b/s32/soc/s32z270/include/Psi5_Ip_Init_PBcfg.h new file mode 100644 index 000000000..ebb7d3182 --- /dev/null +++ b/s32/soc/s32z270/include/Psi5_Ip_Init_PBcfg.h @@ -0,0 +1,92 @@ +/* + * Copyright 2021-2024 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef PSI5_IP_INIT_PBCFG_H +#define PSI5_IP_INIT_PBCFG_H + +/** +* @file Psi5_Ip_Init_PBcfg.h +* +* @addtogroup PSI5_IP PSI5 IPV Driver +* @{ +*/ + +#ifdef __cplusplus +extern "C"{ +#endif + +/*================================================================================================== + INCLUDE FILES + 1) system and project includes + 2) needed interfaces from external units + 3) internal and external interfaces from this unit +==================================================================================================*/ +#include "Psi5_Ip_Types.h" + +/*================================================================================================== + SOURCE FILE VERSION INFORMATION +==================================================================================================*/ +#define PSI5_IP_INIT_PBCFG_VENDOR_ID 43 +#define PSI5_IP_INIT_PBCFG_AR_RELEASE_MAJOR_VERSION 4 +#define PSI5_IP_INIT_PBCFG_AR_RELEASE_MINOR_VERSION 7 +#define PSI5_IP_INIT_PBCFG_AR_RELEASE_REVISION_VERSION 0 +#define PSI5_IP_INIT_PBCFG_SW_MAJOR_VERSION 2 +#define PSI5_IP_INIT_PBCFG_SW_MINOR_VERSION 0 +#define PSI5_IP_INIT_PBCFG_SW_PATCH_VERSION 0 + +/*================================================================================================== +* FILE VERSION CHECKS +==================================================================================================*/ +/* Check if current file and Psi5_Ip_Types.h header file are of the same vendor */ +#if (PSI5_IP_INIT_PBCFG_VENDOR_ID != PSI5_IP_TYPES_VENDOR_ID) + #error "Psi5_Ip_INIT_PBcfg.h and Psi5_Ip_Types.h have different vendor ids" +#endif +/* Check if current file and Psi5_Ip_Types.h header file are of the same Autosar version */ +#if ((PSI5_IP_INIT_PBCFG_AR_RELEASE_MAJOR_VERSION != PSI5_IP_TYPES_AR_RELEASE_MAJOR_VERSION) || \ + (PSI5_IP_INIT_PBCFG_AR_RELEASE_MINOR_VERSION != PSI5_IP_TYPES_AR_RELEASE_MINOR_VERSION) || \ + (PSI5_IP_INIT_PBCFG_AR_RELEASE_REVISION_VERSION != PSI5_IP_TYPES_AR_RELEASE_REVISION_VERSION) \ + ) + #error "AutoSar Version Numbers of Psi5_Ip_INIT_PBcfg.h and Psi5_Ip_Types.h are different" +#endif +/* Check if current file and Psi5_Ip_Types.h header file are of the same software version */ +#if ((PSI5_IP_INIT_PBCFG_SW_MAJOR_VERSION != PSI5_IP_TYPES_SW_MAJOR_VERSION) || \ + (PSI5_IP_INIT_PBCFG_SW_MINOR_VERSION != PSI5_IP_TYPES_SW_MINOR_VERSION) || \ + (PSI5_IP_INIT_PBCFG_SW_PATCH_VERSION != PSI5_IP_TYPES_SW_PATCH_VERSION) \ + ) + #error "Software Version Numbers of Psi5_Ip_INIT_PBcfg.h and Psi5_Ip_Types.h are different" +#endif +/*================================================================================================== +* CONSTANTS +==================================================================================================*/ + +/*================================================================================================== +* DEFINES AND MACROS +==================================================================================================*/ + +/*================================================================================================== +* ENUMS +==================================================================================================*/ + +/*================================================================================================== +* STRUCTURES AND OTHER TYPEDEFS +==================================================================================================*/ + +/*================================================================================================== +* GLOBAL VARIABLE DECLARATIONS +==================================================================================================*/ + +/*================================================================================================== +* FUNCTION PROTOTYPES +==================================================================================================*/ + +#ifdef __cplusplus +} +#endif + +/**@}*/ + +#endif /* PSI5_IP_INIT_PBCFG_H */ + diff --git a/s32/soc/s32z270/src/Clock_Ip_Cfg.c b/s32/soc/s32z270/src/Clock_Ip_Cfg.c index 7086c8a01..20609b306 100644 --- a/s32/soc/s32z270/src/Clock_Ip_Cfg.c +++ b/s32/soc/s32z270/src/Clock_Ip_Cfg.c @@ -945,9 +945,9 @@ static const Clock_Ip_DividerConfigType Clock_Ip_DividerConfigurations_0[CLOCK_I #if CLOCK_IP_CONFIGURED_DIVIDERS_0_NO > 23U { P0_PSI5_189K_CLK, /* name */ - 3306U, /* value */ + 8U, /* value */ { - 2U, + 0U, } }, #endif @@ -1215,9 +1215,9 @@ static const Clock_Ip_DividerConfigType Clock_Ip_DividerConfigurations_0[CLOCK_I #if CLOCK_IP_CONFIGURED_DIVIDERS_0_NO > 50U { P4_PSI5_189K_CLK, /* name */ - 3306U, /* value */ + 8U, /* value */ { - 2U, + 0U, } }, #endif