Inspect BLIF netlist #17
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What is netlist
https://course.ece.cmu.edu/~ee760/760docs/blif.pdf
Verilog source code will be synthesized into a netlist of hardware components(gates or FPGA's LUT), which is the blueprint/schematic of the final hardware implementation.
Open-source FPGA workflow involving netlist
https://community.element14.com/technologies/fpga-group/b/blog/posts/john-beetem-s-arachne-pnr-notes
https://stackoverflow.com/questions/35927650/is-it-possible-to-create-a-simulation-waveform-from-yosys-output
Example1
after
iverilog -o test2.blif -tblif ./test2.v
test2.blif:
You can see it uses generic LUT to implement AND and OR gates.
Example2
after
iverilog -o test2.blif -tblif ./test2.v
Example3
no reset, y will increase by 1 each cycle, otherwise reset to 0;
Note y+1 may only effect y[1], depending on y[0] is 1 or 0.
following command shows schematic and generate following BLIF netlist.
yosys -p 'synth_ice40 -top test -blif test.blif; show' test.v
Analyse result in embedded in following netlist, starting with ###
to understand this netlist, we must know some basic concept:
SB_LUT4
.param LUT_INIT
gives the table content, it's a binary constant, so right-most digit is the last-significant one.=
is net label name connected to the input pinI2=$false
means statically pull-down to 0.use following python code to analyze LUT:
SB_DFFxxx
SB_CARRY
SB_CARRY is the carry-out function of a full adder
convert BLIF back to verilog
yosys can convert BLIF back to standard verilog representation which is essentially the same but more readable:
but the gate's definition (SB_xxx) must be also available to simulate them
following command gives the verilog definition of those SB_xxx ICE40's primitive gates.
for example, we have following definitions in cells_sim.v:
we can see it's still functional definition w/o signal timing information.
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