uvm_test.sublime-snippet

<snippet>
<name>UVM test</name>
<content><![CDATA[class ${1:${TM_FILENAME/(.+)\..+|.*/$1/:name}} extends uvm_test ;
    `uvm_component_utils(${1})

    ${2}_env m_env;
    ${2}_cfg m_cfg;
    $0

    function new(string name = "${2}_test", uvm_component parent=null);
        super.new(name, parent);
    endfunction

    virtual function void build_phase(uvm_phase phase);
        m_env = ${2}_env::type_id::create("${2}_env", this);
        m_cfg = ${2}_cfg::type_id::create("${2}_cfg", this);
        if (!uvm_config_db #(virtual ${2}_if)::get(this, "", "${2}_vif", m_cfgs.${2}_vif))
            `uvm_error(get_type_name(), "Failed to get BFM")
    endfunction

    virtual function void end_of_elaboration_phase(uvm_phase phase);
        uvm_top.print_topology();
        if (!\$value\$plusargs("timeout_clks=%d", timeout_clks)) begin 
            timeout_clks = 500000;
            `uvm_info(get_type_name(), \$sformatf("Illegal timeout value. Setting %0d as the timeout", timeout_clks), UVM_LOW)
        end else if(timeout_clks == 0) begin
            timeout_clks = 500000;
            `uvm_info(get_type_name(), \$sformatf("Got 0 as the timeout. Setting %0d as the timeout", timeout_clks), UVM_LOW)
        end else begin
            `uvm_info(get_type_name(), \$sformatf("Setting %0d as the timeout", timeout_clks), UVM_LOW)            
        end
    endfunction

    virtual task run_phase(uvm_phase phase);
        string seq_names[\$];
        ${2}_base_seq seqs[];
        uvm_cmdline_processor clp = uvm_cmdline_processor::get_inst();
        uvm_factory factory = uvm_factory::get();
        factory.print();

        if (clp.get_arg_values("+SEQ=", seq_names) == 0)
        `uvm_error(get_type_name(), "You didn't specify a sequence to run!")

        seqs = new[seq_names.size()];

        foreach (seq_names[i]) begin
            uvm_object obj;
            obj = factory.create_object_by_name(seq_names[i]);

            if (obj == null)
                `uvm_fatal(get_type_name(),
                    {"Sequence '",seq_names[i],"' not found in factory.",
                        " Was it declared with a `uvm_*_utils macro?"})

            if (!\$cast(seqs[i], obj))
                `uvm_fatal(get_type_name(),
                    {"Sequence '",seq_names[i],"' is not a sequence"})
        end

        ///////////////////////////////////////////////////
        phase.raise_objection(this, "Starting sequences");
        ///////////////////////////////////////////////////
        foreach (seqs[i]) begin
            ${2}_base_seq m_seq = seqs[i];
            `uvm_info(get_type_name(),
                {"Running sequence '",seq_names[i],"'"}, UVM_LOW)
            fork
                begin
                    m_seq.start(null);
                end
                begin
                    repeat (timeout_clks) m_seq.m_cfg.wait_for_pclk();
                    `uvm_fatal(get_type_name(),
                        \$sformatf("\n \t \t ---> TIMEOUT. The test spent more than %0d clks, sorry going to kill it!",timeout_clks))
                end
            join_any
        end
        ///////////////////////////////////////////////////
        phase.drop_objection(this, "Ending sequences");
        ///////////////////////////////////////////////////
                     
    endtask
endclass]]></content>
<tabTrigger>uvm_test</tabTrigger>
<scope>source.systemverilog</scope>
</snippet>