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base repository: ucb-bar/riscv-sodor
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base: ca0431493ec35983388cb08bb203d5e12e9a32b2
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head repository: ucb-bar/riscv-sodor
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compare: 732cbe1990e9ef55ba122664465b372744f2eaab
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  • 1 commit
  • 1 file changed
  • 1 contributor

Commits on Jun 6, 2024

  1. Fix missing prci import

    jerryz123 committed Jun 6, 2024
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    732cbe1 View commit details
Showing with 1 addition and 1 deletion.
  1. +1 −1 src/main/scala/sodor/common/sodor_tile.scala
2 changes: 1 addition & 1 deletion src/main/scala/sodor/common/sodor_tile.scala
Original file line number Diff line number Diff line change
@@ -14,7 +14,7 @@ import freechips.rocketchip.interrupts._
import freechips.rocketchip.util._
import freechips.rocketchip.tile._
import freechips.rocketchip.amba.axi4._
import freechips.rocketchip.prci.ClockSinkParameters
import freechips.rocketchip.prci._

// Example parameter class copied from Ariane, not included in documentation but for compile check only
// If you are here for documentation, DO NOT copy MyCoreParams and MyTileParams directly - always figure