diff --git a/build.sbt b/build.sbt index 0976a5e6ea..c0bc6d8543 100644 --- a/build.sbt +++ b/build.sbt @@ -98,8 +98,8 @@ lazy val chisel6Settings = Seq( addCompilerPlugin("org.chipsalliance" % "chisel-plugin" % "6.0.0" cross CrossVersion.full) ) lazy val chisel3Settings = Seq( - libraryDependencies ++= Seq("edu.berkeley.cs" %% "chisel3" % "3.6.0"), - addCompilerPlugin("edu.berkeley.cs" % "chisel3-plugin" % "3.6.0" cross CrossVersion.full) + libraryDependencies ++= Seq("edu.berkeley.cs" %% "chisel3" % "3.6.1"), + addCompilerPlugin("edu.berkeley.cs" % "chisel3-plugin" % "3.6.1" cross CrossVersion.full) ) lazy val chiselSettings = (if (chisel6) chisel6Settings else chisel3Settings) ++ Seq( diff --git a/generators/chipyard/src/main/scala/clocking/ClockBinders.scala b/generators/chipyard/src/main/scala/clocking/ClockBinders.scala index bcf2fb4907..7ef9f9227a 100644 --- a/generators/chipyard/src/main/scala/clocking/ClockBinders.scala +++ b/generators/chipyard/src/main/scala/clocking/ClockBinders.scala @@ -27,9 +27,9 @@ class WithPLLSelectorDividerClockGenerator(enable: Boolean = true) extends Overr val clockSelector = system.prci_ctrl_domain { LazyModule(new TLClockSelector(baseAddress + 0x30000, tlbus.beatBytes, enable=enable)) } val pllCtrl = system.prci_ctrl_domain { LazyModule(new FakePLLCtrl (baseAddress + 0x40000, tlbus.beatBytes)) } - clockDivider.tlNode := system.prci_ctrl_domain { TLFragmenter(tlbus.beatBytes, tlbus.blockBytes) := system.prci_ctrl_bus.get } - clockSelector.tlNode := system.prci_ctrl_domain { TLFragmenter(tlbus.beatBytes, tlbus.blockBytes) := system.prci_ctrl_bus.get } - pllCtrl.tlNode := system.prci_ctrl_domain { TLFragmenter(tlbus.beatBytes, tlbus.blockBytes) := system.prci_ctrl_bus.get } + clockDivider.tlNode := system.prci_ctrl_domain { TLFragmenter(tlbus, Some("ClockDivider")) := system.prci_ctrl_bus.get } + clockSelector.tlNode := system.prci_ctrl_domain { TLFragmenter(tlbus, Some("ClockSelector")) := system.prci_ctrl_bus.get } + pllCtrl.tlNode := system.prci_ctrl_domain { TLFragmenter(tlbus, Some("PLLCtrl")) := system.prci_ctrl_bus.get } system.chiptopClockGroupsNode := clockDivider.clockNode := clockSelector.clockNode diff --git a/generators/chipyard/src/main/scala/clocking/ClockGroupNamePrefixer.scala b/generators/chipyard/src/main/scala/clocking/ClockGroupNamePrefixer.scala index 08d54acf15..367386a1a7 100644 --- a/generators/chipyard/src/main/scala/clocking/ClockGroupNamePrefixer.scala +++ b/generators/chipyard/src/main/scala/clocking/ClockGroupNamePrefixer.scala @@ -28,6 +28,7 @@ class ClockGroupParameterModifier( sinkFn: ClockGroupSinkParameters => ClockGroupSinkParameters = { s => s })( implicit p: Parameters, v: ValName) extends LazyModule { val node = ClockGroupAdapterNode(sourceFn, sinkFn) + override def shouldBeInlined = true lazy val module = new LazyRawModuleImp(this) { (node.out zip node.in).map { case ((o, _), (i, _)) => (o.member.data zip i.member.data).foreach { case (oD, iD) => oD := iD } diff --git a/generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala b/generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala index d4b36b5053..f1936d487c 100644 --- a/generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala +++ b/generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala @@ -40,7 +40,7 @@ trait HasChipyardPRCI { this: BaseSubsystem with InstantiatesHierarchicalElement val prci_ctrl_domain = tlbus.generateSynchronousDomain("ChipyardPRCICtrl") .suggestName("chipyard_prcictrl_domain") - val prci_ctrl_bus = Option.when(prciParams.generatePRCIXBar) { prci_ctrl_domain { TLXbar() } } + val prci_ctrl_bus = Option.when(prciParams.generatePRCIXBar) { prci_ctrl_domain { TLXbar(nameSuffix = Some("prcibus")) } } prci_ctrl_bus.foreach(xbar => tlbus.coupleTo("prci_ctrl") { (xbar := TLFIFOFixer(TLFIFOFixer.all) := TLBuffer() @@ -71,13 +71,13 @@ trait HasChipyardPRCI { this: BaseSubsystem with InstantiatesHierarchicalElement } val tileClockGater = Option.when(prciParams.enableTileClockGating) { prci_ctrl_domain { val clock_gater = LazyModule(new TileClockGater(prciParams.baseAddress + 0x00000, tlbus.beatBytes)) - clock_gater.tlNode := TLFragmenter(tlbus.beatBytes, tlbus.blockBytes) := prci_ctrl_bus.get + clock_gater.tlNode := TLFragmenter(tlbus.beatBytes, tlbus.blockBytes, nameSuffix = Some("TileClockGater")) := prci_ctrl_bus.get clock_gater } } val tileResetSetter = Option.when(prciParams.enableTileResetSetting) { prci_ctrl_domain { val reset_setter = LazyModule(new TileResetSetter(prciParams.baseAddress + 0x10000, tlbus.beatBytes, tile_prci_domains.map(_._2.tile_reset_domain.clockNode.portParams(0).name.get).toSeq, Nil)) - reset_setter.tlNode := TLFragmenter(tlbus.beatBytes, tlbus.blockBytes) := prci_ctrl_bus.get + reset_setter.tlNode := TLFragmenter(tlbus.beatBytes, tlbus.blockBytes, nameSuffix = Some("TileResetSetter")) := prci_ctrl_bus.get reset_setter } } diff --git a/generators/chipyard/src/main/scala/config/AbstractConfig.scala b/generators/chipyard/src/main/scala/config/AbstractConfig.scala index 11d70982c5..ff65ad892f 100644 --- a/generators/chipyard/src/main/scala/config/AbstractConfig.scala +++ b/generators/chipyard/src/main/scala/config/AbstractConfig.scala @@ -123,7 +123,6 @@ class AbstractConfig extends Config( new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ /** hierarchical buses including sbus/mbus/pbus/fbus/cbus/l2 */ new chipyard.config.WithSV48IfPossible ++ /** use sv48 if possible */ - // ================================================ // Set up power, reset and clocking // ================================================ diff --git a/generators/chipyard/src/main/scala/config/NoCoreConfigs.scala b/generators/chipyard/src/main/scala/config/NoCoreConfigs.scala index 23da970050..5f376eaa8b 100644 --- a/generators/chipyard/src/main/scala/config/NoCoreConfigs.scala +++ b/generators/chipyard/src/main/scala/config/NoCoreConfigs.scala @@ -13,9 +13,9 @@ class NoCoresConfig extends Config( new chipyard.config.WithNoUART ++ new chipyard.config.WithNoTileClockGaters ++ new chipyard.config.WithNoTileResetSetters ++ - new chipyard.config.WithNoBusErrorDevices ++ new chipyard.config.WithNoDebug ++ new chipyard.config.WithNoPLIC ++ + new chipyard.config.WithNoBusErrorDevices ++ new chipyard.config.AbstractConfig) // A config that uses a empty chiptop module with no rocket-chip soc components diff --git a/generators/diplomacy b/generators/diplomacy index 055be698f4..6b7dc988a7 160000 --- a/generators/diplomacy +++ b/generators/diplomacy @@ -1 +1 @@ -Subproject commit 055be698f4ad55bf4a90b3d5e31d4344be5f788b +Subproject commit 6b7dc988a771ff21237b102fd02a1f2d2c2e7b72 diff --git a/generators/hardfloat b/generators/hardfloat index d93aa57080..4225367ed2 160000 --- a/generators/hardfloat +++ b/generators/hardfloat @@ -1 +1 @@ -Subproject commit d93aa570806013dea479a92ba9bb33d1f2d4f69f +Subproject commit 4225367ed282aadd70f4cbd131f6959f4d00c502 diff --git a/generators/rocket-chip b/generators/rocket-chip index 4ac1529d98..ea9979b1c6 160000 --- a/generators/rocket-chip +++ b/generators/rocket-chip @@ -1 +1 @@ -Subproject commit 4ac1529d982df90da6970c1425ec471e304ba4fb +Subproject commit ea9979b1c6e3cc078a6efe1f58012180753c5ec8 diff --git a/generators/rocket-chip-blocks b/generators/rocket-chip-blocks index c667be9bb3..c8c14f7b47 160000 --- a/generators/rocket-chip-blocks +++ b/generators/rocket-chip-blocks @@ -1 +1 @@ -Subproject commit c667be9bb32f25e52516e71cd1ded58290ac5993 +Subproject commit c8c14f7b47c3c790022c293bc7e4309f5c5ed523 diff --git a/generators/rocket-chip-inclusive-cache b/generators/rocket-chip-inclusive-cache index 45d184f2fd..4aab5460bd 160000 --- a/generators/rocket-chip-inclusive-cache +++ b/generators/rocket-chip-inclusive-cache @@ -1 +1 @@ -Subproject commit 45d184f2fd1e2189d6302468e208a054b681caab +Subproject commit 4aab5460bd569b2142eb760e4772ea8db6998dc3 diff --git a/generators/testchipip b/generators/testchipip index b85f5ac046..5856bedf49 160000 --- a/generators/testchipip +++ b/generators/testchipip @@ -1 +1 @@ -Subproject commit b85f5ac0464d16706000c6b1ef5b0c8556f84133 +Subproject commit 5856bedf495188a95934969eac19a5fd9534bb0a diff --git a/sims/firesim b/sims/firesim index 23346f12dc..c95e7fbc8d 160000 --- a/sims/firesim +++ b/sims/firesim @@ -1 +1 @@ -Subproject commit 23346f12dcfd76125dd1d5bec162b72bf9f7d97b +Subproject commit c95e7fbc8d4de833874338b2a7f14ab4dbd979f1