diff --git a/.github/scripts/check-commit.sh b/.github/scripts/check-commit.sh index 1b859414f8..e906ac29b2 100755 --- a/.github/scripts/check-commit.sh +++ b/.github/scripts/check-commit.sh @@ -46,7 +46,7 @@ search () { } -submodules=("cva6" "boom" "ibex" "gemmini" "icenet" "nvdla" "rocket-chip" "rocket-chip-blocks" "rocket-chip-inclusive-cache" "testchipip" "riscv-sodor" "mempress" "bar-fetchers" "shuttle" "constellation" "fft-generator" "hardfloat" "caliptra-aes-acc" "rocc-acc-utils" "diplomacy" "rerocc") +submodules=("cva6" "boom" "ibex" "gemmini" "icenet" "nvdla" "rocket-chip" "rocket-chip-blocks" "rocket-chip-inclusive-cache" "testchipip" "riscv-sodor" "mempress" "bar-fetchers" "shuttle" "constellation" "fft-generator" "hardfloat" "caliptra-aes-acc" "rocc-acc-utils" "diplomacy" "rerocc" "compress-acc") dir="generators" branches=("master" "main" "dev") search diff --git a/.github/scripts/defaults.sh b/.github/scripts/defaults.sh index d76d7a32ec..0533846a16 100755 --- a/.github/scripts/defaults.sh +++ b/.github/scripts/defaults.sh @@ -30,7 +30,7 @@ REMOTE_COURSIER_CACHE=$REMOTE_WORK_DIR/.coursier-cache declare -A grouping grouping["group-cores"]="chipyard-cva6 chipyard-ibex chipyard-rocket chipyard-hetero chipyard-boomv3 chipyard-boomv4 chipyard-sodor chipyard-digitaltop chipyard-multiclock-rocket chipyard-nomem-scratchpad chipyard-spike chipyard-clone chipyard-prefetchers chipyard-shuttle" grouping["group-peripherals"]="chipyard-dmirocket chipyard-dmiboomv3 chipyard-dmiboomv4 chipyard-spiflashwrite chipyard-mmios chipyard-nocores chipyard-manyperipherals chipyard-chiplike chipyard-tethered chipyard-symmetric chipyard-llcchiplet" -grouping["group-accels"]="chipyard-mempress chipyard-gemmini chipyard-manymmioaccels chipyard-nvdla chipyard-aes256ecb chipyard-rerocc" +grouping["group-accels"]="chipyard-compressacc chipyard-mempress chipyard-gemmini chipyard-manymmioaccels chipyard-nvdla chipyard-aes256ecb chipyard-rerocc" grouping["group-constellation"]="chipyard-constellation" grouping["group-tracegen"]="tracegen tracegen-boomv3 tracegen-boomv4" grouping["group-other"]="icenet testchipip constellation rocketchip-amba rocketchip-tlsimple rocketchip-tlwidth rocketchip-tlxbar chipyard-clusters" @@ -41,6 +41,7 @@ declare -A mapping mapping["chipyard-rocket"]=" CONFIG=QuadChannelRocketConfig" mapping["chipyard-dmirocket"]=" CONFIG=dmiRocketConfig" mapping["chipyard-mempress"]=" CONFIG=MempressRocketConfig" +mapping["chipyard-compressacc"]=" CONFIG=ZstdCompressorRocketConfig" mapping["chipyard-prefetchers"]=" CONFIG=PrefetchingRocketConfig" mapping["chipyard-digitaltop"]=" TOP=DigitalTop" mapping["chipyard-manymmioaccels"]=" CONFIG=ManyMMIOAcceleratorRocketConfig" diff --git a/.github/scripts/run-tests.sh b/.github/scripts/run-tests.sh index 90fe0687a3..6855e15a2b 100755 --- a/.github/scripts/run-tests.sh +++ b/.github/scripts/run-tests.sh @@ -72,7 +72,7 @@ case $1 in run_bmark ;; chipyard-prefetchers) - run_binary BINARY=$RISCV/riscv64-unknown-elf/share/riscv-tests/benchmarks/dhrystone.riscv + run_binary BINARY=$RISCV/riscv64-unknown-elf/share/riscv-tests/benchmarks/dhrystone.riscv LOADMEM=1 ;; rocketchip) run_bmark @@ -81,13 +81,17 @@ case $1 in GEMMINI_SOFTWARE_DIR=$LOCAL_SIM_DIR/../../generators/gemmini/software/gemmini-rocc-tests rm -rf $GEMMINI_SOFTWARE_DIR/riscv-tests cd $LOCAL_SIM_DIR - run_binary BINARY=$GEMMINI_SOFTWARE_DIR/build/bareMetalC/aligned-baremetal - run_binary BINARY=$GEMMINI_SOFTWARE_DIR/build/bareMetalC/raw_hazard-baremetal - run_binary BINARY=$GEMMINI_SOFTWARE_DIR/build/bareMetalC/mvin_mvout-baremetal + run_binary BINARY=$GEMMINI_SOFTWARE_DIR/build/bareMetalC/aligned-baremetal LOADMEM=1 + run_binary BINARY=$GEMMINI_SOFTWARE_DIR/build/bareMetalC/raw_hazard-baremetal LOADMEM=1 + run_binary BINARY=$GEMMINI_SOFTWARE_DIR/build/bareMetalC/mvin_mvout-baremetal LOADMEM=1 ;; chipyard-mempress) (cd $LOCAL_CHIPYARD_DIR/generators/mempress/software/src && make) - run_binary BINARY=$LOCAL_CHIPYARD_DIR/generators/mempress/software/src/mempress-rocc.riscv + run_binary BINARY=$LOCAL_CHIPYARD_DIR/generators/mempress/software/src/mempress-rocc.riscv LOADMEM=1 + ;; + chipyard-compressacc) + (cd $LOCAL_CHIPYARD_DIR/generators/compress-acc/software-zstd/compress && ./build-hcb-single-file.sh) + run_binary BINARY=$LOCAL_CHIPYARD_DIR/generators/compress-acc/software-zstd/compress/009987_cl0_ws12.riscv LOADMEM=1 ;; chipyard-manymmioaccels) make -C $LOCAL_CHIPYARD_DIR/tests diff --git a/.github/workflows/chipyard-run-tests.yml b/.github/workflows/chipyard-run-tests.yml index 24654306a6..d86c75c907 100644 --- a/.github/workflows/chipyard-run-tests.yml +++ b/.github/workflows/chipyard-run-tests.yml @@ -892,6 +892,29 @@ jobs: group-key: "group-accels" project-key: "chipyard-mempress" + chipyard-compressacc-run-tests: + name: chipyard-compressacc-run-tests + needs: prepare-chipyard-accels + runs-on: as4 + steps: + - name: Delete old checkout + run: | + ls -alh . + rm -rf ${{ github.workspace }}/* || true + rm -rf ${{ github.workspace }}/.* || true + ls -alh . + - name: Checkout + uses: actions/checkout@v3 + - name: Git workaround + uses: ./.github/actions/git-workaround + - name: Create conda env + uses: ./.github/actions/create-conda-env + - name: Run tests + uses: ./.github/actions/run-tests + with: + group-key: "group-accels" + project-key: "chipyard-compressacc" + tracegen-boomv3-run-tests: name: tracegen-boomv3-run-tests @@ -1171,6 +1194,7 @@ jobs: chipyard-manymmioaccels-run-tests, # chipyard-nvdla-run-tests, chipyard-prefetchers-run-tests, chipyard-mempress-run-tests, + chipyard-compressacc-run-tests, chipyard-constellation-run-tests, tracegen-boomv3-run-tests, tracegen-boomv4-run-tests, diff --git a/.gitmodules b/.gitmodules index c24ded763c..6ff8ac86f1 100644 --- a/.gitmodules +++ b/.gitmodules @@ -145,3 +145,6 @@ [submodule "generators/rerocc"] path = generators/rerocc url = https://github.com/ucb-bar/rerocc.git +[submodule "generators/compress-acc"] + path = generators/compress-acc + url = https://github.com/ucb-bar/compress-acc.git diff --git a/build.sbt b/build.sbt index 36bf77420f..0976a5e6ea 100644 --- a/build.sbt +++ b/build.sbt @@ -173,7 +173,8 @@ lazy val chipyard = (project in file("generators/chipyard")) .dependsOn(testchipip, rocketchip, boom, rocketchip_blocks, rocketchip_inclusive_cache, dsptools, rocket_dsp_utils, gemmini, icenet, tracegen, cva6, nvdla, sodor, ibex, fft_generator, - constellation, mempress, barf, shuttle, caliptra_aes, rerocc) + constellation, mempress, barf, shuttle, caliptra_aes, rerocc, + compressacc) .settings(libraryDependencies ++= rocketLibDeps.value) .settings( libraryDependencies ++= Seq( @@ -183,6 +184,11 @@ lazy val chipyard = (project in file("generators/chipyard")) .settings(commonSettings) .settings(Compile / unmanagedSourceDirectories += file(stageDir)) +lazy val compressacc = (project in file("generators/compress-acc")) + .dependsOn(rocketchip) + .settings(libraryDependencies ++= rocketLibDeps.value) + .settings(commonSettings) + lazy val mempress = (project in file("generators/mempress")) .dependsOn(rocketchip) .settings(libraryDependencies ++= rocketLibDeps.value) diff --git a/docs/Generators/CompressAcc.rst b/docs/Generators/CompressAcc.rst new file mode 100644 index 0000000000..b18b47092f --- /dev/null +++ b/docs/Generators/CompressAcc.rst @@ -0,0 +1,6 @@ +CompressAcc +==================================== + +We have (de)compression accelerators for two major compression algorithms : Snappy(`Snappy Github `__) and ZStd(`ZStd Github `__). + +For more information, check out the CDPU paper: `CDPU: Co-designing Compression and Decompression Processing Units for Hyperscale Systems `__ . diff --git a/docs/Generators/index.rst b/docs/Generators/index.rst index 88d9ee2a0b..d55dce0cc8 100644 --- a/docs/Generators/index.rst +++ b/docs/Generators/index.rst @@ -33,4 +33,5 @@ so changes to the generators themselves will automatically be used when building Sodor Shuttle Mempress + CompressAcc Prefetchers diff --git a/generators/chipyard/src/main/scala/config/RoCCAcceleratorConfigs.scala b/generators/chipyard/src/main/scala/config/RoCCAcceleratorConfigs.scala index 91ee7c15ce..960872b12b 100644 --- a/generators/chipyard/src/main/scala/config/RoCCAcceleratorConfigs.scala +++ b/generators/chipyard/src/main/scala/config/RoCCAcceleratorConfigs.scala @@ -67,3 +67,8 @@ class ReRoCCManyGemminiConfig extends Config( new gemmini.LeanGemminiConfig ++ // rerocc tile0 is gemmini new freechips.rocketchip.subsystem.WithNBigCores(4) ++ // 4 rocket cores new chipyard.config.AbstractConfig) + +class ZstdCompressorRocketConfig extends Config( + new compressacc.WithZstdCompressor ++ + new freechips.rocketchip.subsystem.WithNBigCores(1) ++ + new chipyard.config.AbstractConfig) diff --git a/generators/compress-acc b/generators/compress-acc new file mode 160000 index 0000000000..580fc99a8d --- /dev/null +++ b/generators/compress-acc @@ -0,0 +1 @@ +Subproject commit 580fc99a8de7e6965c5bc9f08945bc854d7d2a0c