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base repository: ucb-bar/berkeley-hardfloat
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base: d93aa570806013dea479a92ba9bb33d1f2d4f69f
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head repository: ucb-bar/berkeley-hardfloat
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compare: 4225367ed282aadd70f4cbd131f6959f4d00c502
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  • 3 commits
  • 7 files changed
  • 3 contributors

Commits on Oct 20, 2023

  1. Update resizeRawFloat.scala (#80)

    This code would actually cause an "high index XX is out of range" error
    FJShen authored Oct 20, 2023
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    cdb51a7 View commit details

Commits on Oct 26, 2023

  1. Update testfloat.nix (#81)

    sequencer authored Oct 26, 2023
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    b3c8a38 View commit details

Commits on Jun 5, 2024

  1. Copy the full SHA
    4225367 View commit details
3 changes: 3 additions & 0 deletions hardfloat/src/main/scala/DivSqrtRecFN_small.scala
Original file line number Diff line number Diff line change
@@ -199,6 +199,7 @@ class
DivSqrtRawFN_small(expWidth: Int, sigWidth: Int, options: Int)
extends Module
{
override def desiredName = s"DivSqrtRawFN_small_e${expWidth}_s${sigWidth}"
val io = IO(new Bundle {
/*--------------------------------------------------------------------
*--------------------------------------------------------------------*/
@@ -421,6 +422,7 @@ class
DivSqrtRecFNToRaw_small(expWidth: Int, sigWidth: Int, options: Int)
extends Module
{
override def desiredName = s"DivSqrtRecFMToRaw_small_e${expWidth}_s${sigWidth}"
val io = IO(new Bundle {
/*--------------------------------------------------------------------
*--------------------------------------------------------------------*/
@@ -466,6 +468,7 @@ class
DivSqrtRecFN_small(expWidth: Int, sigWidth: Int, options: Int)
extends Module
{
override def desiredName = s"DivSqrtRecFM_small_e${expWidth}_s${sigWidth}"
val io = IO(new Bundle {
/*--------------------------------------------------------------------
*--------------------------------------------------------------------*/
1 change: 1 addition & 0 deletions hardfloat/src/main/scala/INToRecFN.scala
Original file line number Diff line number Diff line change
@@ -42,6 +42,7 @@ import consts._

class INToRecFN(intWidth: Int, expWidth: Int, sigWidth: Int) extends RawModule
{
override def desiredName = s"INToRecFN_i${intWidth}_e${expWidth}_s${sigWidth}"
val io = IO(new Bundle {
val signedIn = Input(Bool())
val in = Input(Bits(intWidth.W))
3 changes: 3 additions & 0 deletions hardfloat/src/main/scala/MulAddRecFN.scala
Original file line number Diff line number Diff line change
@@ -70,6 +70,7 @@ class MulAddRecFN_interIo(expWidth: Int, sigWidth: Int) extends Bundle
//----------------------------------------------------------------------------
class MulAddRecFNToRaw_preMul(expWidth: Int, sigWidth: Int) extends RawModule
{
override def desiredName = s"MulAddRecFNToRaw_preMul_e${expWidth}_s${sigWidth}"
val io = IO(new Bundle {
val op = Input(Bits(2.W))
val a = Input(Bits((expWidth + sigWidth + 1).W))
@@ -167,6 +168,7 @@ class MulAddRecFNToRaw_preMul(expWidth: Int, sigWidth: Int) extends RawModule
//----------------------------------------------------------------------------
class MulAddRecFNToRaw_postMul(expWidth: Int, sigWidth: Int) extends RawModule
{
override def desiredName = s"MulAddRecFNToRaw_postMul_e${expWidth}_s${sigWidth}"
val io = IO(new Bundle {
val fromPreMul = Input(new MulAddRecFN_interIo(expWidth, sigWidth))
val mulAddResult = Input(UInt((sigWidth * 2 + 1).W))
@@ -297,6 +299,7 @@ class MulAddRecFNToRaw_postMul(expWidth: Int, sigWidth: Int) extends RawModule

class MulAddRecFN(expWidth: Int, sigWidth: Int) extends RawModule
{
override def desiredName = s"MulAddRecFN_e${expWidth}_s${sigWidth}"
val io = IO(new Bundle {
val op = Input(Bits(2.W))
val a = Input(Bits((expWidth + sigWidth + 1).W))
1 change: 1 addition & 0 deletions hardfloat/src/main/scala/RecFNToIN.scala
Original file line number Diff line number Diff line change
@@ -45,6 +45,7 @@ import consts._

class RecFNToIN(expWidth: Int, sigWidth: Int, intWidth: Int) extends chisel3.Module
{
override def desiredName = s"RecFNToIN_e${expWidth}_s${sigWidth}_i${intWidth}"
val io = IO(new Bundle {
val in = Input(Bits((expWidth + sigWidth + 1).W))
val roundingMode = Input(UInt(3.W))
2 changes: 2 additions & 0 deletions hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala
Original file line number Diff line number Diff line change
@@ -54,6 +54,7 @@ class
)
extends RawModule
{
override def desiredName = s"RoundAnyRawFNToRecFN_ie${inExpWidth}_is${inSigWidth}_oe${outExpWidth}_os${outSigWidth}"
val io = IO(new Bundle {
val invalidExc = Input(Bool()) // overrides 'infiniteExc' and 'in'
val infiniteExc = Input(Bool()) // overrides 'in' except for 'in.sign'
@@ -294,6 +295,7 @@ class
RoundRawFNToRecFN(expWidth: Int, sigWidth: Int, options: Int)
extends RawModule
{
override def desiredName = s"RoundRawFNToRecFN_e${expWidth}_s${sigWidth}"
val io = IO(new Bundle {
val invalidExc = Input(Bool()) // overrides 'infiniteExc' and 'in'
val infiniteExc = Input(Bool()) // overrides 'in' except for 'in.sign'
2 changes: 1 addition & 1 deletion hardfloat/src/main/scala/resizeRawFloat.scala
Original file line number Diff line number Diff line change
@@ -69,7 +69,7 @@ object resizeRawFloat
(if (in.sigWidth <= sigWidth)
in.sig<<(sigWidth - in.sigWidth)
else
in.sig(in.sigWidth + 2, in.sigWidth - sigWidth + 1) ##
in.sig(in.sigWidth, in.sigWidth - sigWidth + 1) ##
in.sig(in.sigWidth - sigWidth, 0).orR
)
out
2 changes: 1 addition & 1 deletion nix/testfloat.nix
Original file line number Diff line number Diff line change
@@ -1,6 +1,6 @@
{ stdenv, fetchFromGitHub, softfloat }:
stdenv.mkDerivation rec {
pname = "softfloat";
pname = "testfloat";
version = "06b20075dd3c1a5d0dd007a93643282832221612";
src = fetchFromGitHub {
owner = "ucb-bar";