Board completely routed - 2022/08/18

[josuah]

https://cdn.discordapp.com/attachments/985342148884987934/1009574670934229083/pico-ice_layout.pdf

[josuah]

Ground layer barely used for signal, +3v3 much more used
This is likely a feature if ground can be considered as part of the signal: that way, the vias permit the current to move freely on the entire uninterrupted ground plane.

[vr2045]

I like to use a solid ground plane. All signals & power are referred to a solid sheet, significantly reducing the chances of strange issues.

[josuah]

That teaches me something about grounding. 4-layers PCBs are really nice

[josuah]

No separate "analog" Ground pin

On the "pico" board:

But looking at the pico board itself:

The "AGND" pin seems bound to the same global ground pad as all the others.
Maybe it is only used for the passives used for the reference voltage...
Or maybe it is there for promoting good practices.

The RP2040 chip does not seem to have any separate ground plane than the big pad.
We are probably good.

[vr2045]

Yes, they seem to have tied off the ground to a common (and split) ground plane. I think a solid ground will help. This will likely cause some issues for the ADC by adding noise. Will have to wait and see if this really affects the ADC...

[josuah]

[josuah]

My bad, these are the RESISTORS for the LED, not the LED itself...

[josuah]

Part reuse for USB
The USB standard permits two 10k resistor to be put in parallel (5.0k) instead of the 5.1k, given the error margin of a few percents in the spec.
This would permit to kill the 5.1k off the BOM.

[josuah]

Given the board situation above, there would be a via needed for the two 10k in parallel, or 4 * 10k resistors in total (2 for CC1, 2 for CC2).

A via would not hurt the CC pin a lot: not a signal pin: mostly constant if not used.

[vr2045]

Good idea to look into DFM at this stage.
In this particular case, resistor cost is far smaller than placement cost or that of an additional part to be managed given that its a common one. So given a choice, I would replace multiple resistors with a single one, not vice-versa.

[josuah]

Overview of the JTAG header

Is it meant to have something soldered in there? Anything in mind? Yes! As seen below.

[josuah]

Here goes the header. It could be a bit inconvenient in breadboard mode: bottom of the board... But who needs breadboard when you have PMODs!

[josuah]

It would be handy to have a link toward a cable for sell matching the header.
And a clear pinout:

│o o              o o │
│o o              o o │
│o o < BACKSIDE > o o │
│o o              o o │  ┌────────────────────────────┐
│o o              o o │ /│                            │
│o o              o o │/ │                            │
│  _                  /  │    GND  x  GND GND 3V3     │
│────'┬────┬ ┌───────┐│  │ ┌───│───│───│───│───│───┐  │
│BOOT ┤°   ├ │┌┴┴┴┴└┐││  │ │   o   o   o   o   o   │  │
│o    ┤    ├ ││:::::│││  │ │                       │  │
│o    ┴────┴ │└┬┬┬┬┬┘││  │ │   o   o   o   o   o   │  │
│-      U2   └───────┘│  │ └───│───│───│───│───│───┘  │
│      O       O      \  │    RST  x   x  SWC SWD     │
│ _   PICO-ICE v1   _ │\ │                            │
│(_)   O       O   (_)│ \│                            │
└─────────────────────┘  └────────────────────────────┘

^ is this correct?

[josuah]

iCE40 FPGAs do not have a JTAG interface -- [https://stackoverflow.com/questions/49840479/lattice-ice40-jtag#49844398](Claire Clifford)

And maybe along with a note that the JTAG is only for the RP2040.

[vr2045]

Right, you got it! This connector is pretty standard and compact. Anyone doing work with embedded processors has likely got one of these lying around or has access to one so I selected this.
The RPi foundation made up a smaller connector but I dont see that as a standard yet, it just might become prevalent in which case, I'll replace this. This connector wont be installed by default.

[josuah]

BOM overview
Filtering components with 3 or less instances, we have mostly connectors or chips, and a few usual passives (marked with *, with S for solved):

1       :SW_Push_1 PTS820 J25K SMTR LFS (SW2)
1       Connector:Conn_ARM_JTAG_SWD_10 Conn_ARM_JTAG_SWD_10 (J5)
1       Connector:USB_C_Receptacle_USB2.0 USB_C_Receptacle_USB2.0 (J1)
1       Connector_Generic:Conn_01x02 BOOT_SEL (J9)
1       Device:Crystal_GND24 12 MHz (Y1)
1       Regulator_Linear:NCP1117-3.3_SOT223 NCP1117ST33T3G (U1)
1       Switch:SW_Push PTS820 J25K SMTR LFS (SW1)
1       UPduino_v3.0:AP2127K-1.2 CL9293A12L5M (U4)
1       UPduino_v3.0:Connector_TestPoint TestPoint (TP1)
1       UPduino_v3.0:Device_LED_ALT LTST-C191KGKT (D3)
1  * S  UPduino_v3.0:Device_R 100 (R11)
1       UPduino_v3.0:Device_R MF-FSMF035X-2 (PTC1)
1       UPduino_v3.0:Device_R OPEN (SJ6)
1  *    UPduino_v3.0:Diode_1N4148W 1N4148WT-7 (D1)
1       UPduino_v3.0:ICE40UP5K-SG48ITR-FPGA_Lattice ICE40UP5K-SG48ITR (U6)
1       UPduino_v3.0:W25Q32JVSS-Memory_Flash APS6404L-3SQN-SN (U5)
1       pico-ice_minimal:MCU_RaspberryPi_RP2040_RP2040 RP2040 (U3)
2       2x3FemaleHeader:2x3_2.54mm_Female 2x3_2.54mm_Female (J10, J11)
2  * S  Device:C 1u (C6, C11)
2  * S  Device:C 27p (C1, C2)
2  * S  Device:R 1k (R1, R2)
2       UPduino_v3.0:Device_LED_ARGB MHPA1010RGBDT (D2, D4)
2  * S  UPduino_v3.0:Device_R 5.1K (R10, R24)
2       UPduino_v3.0:W25Q32JVSS-Memory_Flash W25Q32JVSSIQ (U2, U8)
3       UPduino_v3.0:Device_R SHORT (SJ1, SJ4, SJ5)

P.S.: no need to read everything below, the BOM looks good.

[josuah]

R11 (solved)

As written in the ICE40 sysCLOCK PLL guide: https://www.latticesemi.com/-/media/LatticeSemi/Documents/ApplicationNotes/IK2/FPGA-TN-02052-1-3-iCE40-sysCLOCK-PLL-Design-Usage-Guide.ashx

As I understand it, there should be some "GNDPLL" pin on the ICE40 but...

No trace of GNDPLL in https://www.latticesemi.com/view_document?document_id=51971

Confirmed by EEVblog:

The trick is the ice40UP5k in SG48 packages does not possess the GNDPLL pin. The appnote says the PLL's decoupling filter shall be wired between VCCPLL and GNDPLL, and "GNDPLL must not be connected to the board's ground". They want to minimize the noise getting into the PLL, therefore in other packages the special GNDPLL pin is directly connected to the internal sensitive PLL circuitry..
As the SG48 got only a single GND at its thermal pad the pcb designers are in doubt where to wire the decoupling capacitors, it seems.. -- https://www.eevblog.com/forum/microcontrollers/8$-ice40-developer-board/msg1396333/#msg1396333

[josuah]

D1

Q: I cannot see why it is current would be let flowing between these two power rails: would that not heat-up the device to have a short there?

Although, not much current: between 1mA and 10mA if I read it right:

-- https://www.vishay.com/docs/85748/1n4148w.pdf

[josuah]

C11 and C6 (solved)

Hardly any closer to the RP2040

Could be made 4.7uF for reducing the BOM, deviating only slightly from the recommendation, but for the main input power, probably good to use slightly higher values.

-- https://datasheets.raspberrypi.com/rp2040/hardware-design-with-rp2040.pdf#page=7

[josuah]

C1 and C2 and R1 (solved)

Could be made 0.1uF (100pF) instead of 27pF, but here it is not about stability, but filtering for a crystal. Probably better let as recommended.

R1 is 1k, but also part of that filter.

[josuah]

R2 (solved)

R2 is 1k, same as R1 and reason is expained in https://datasheets.raspberrypi.com/rp2040/hardware-design-with-rp2040.pdf#page=9 :

R2 is marked as DNF (Do Not Fit) on the schematic, as we have found that with this particular flash device, the external pull-up is unnecessary. However, if a different flash is used, it may become important to be able to insert a 10kΩ resistor here, so it has been included just in case.

[josuah]

15-pin headers vs 16-pin header
@e2k said on the chat server:

probably a stupid remark, but I always try to use connectors of "standard"sizes ... You used 15x2, 16x2 is easier to get ... I know, you can cut the yourself, but than again, the 32x2 is a standard ... (by standard I mean, that there is usually more of them in stock)

[josuah]

I think these are two regular 6x2 (as used in PMOD) headers, as well as one 3x2 header in-between the two PMODs

Which would help with figuring out where each PMOD starts: by having discontinuity in the header plastic acting as markings.

Visually, it is more obvious that the PMODs are at the left and right
here |_______|___|_______| than
here |___________________|

[josuah]

NCP1117ST33T3G is out of stock on Digikey and Mouser**
https://www.digikey.com/en/products/detail/onsemi/ncp1117st33t3g/1749063
https://www.mouser.fr/ProductDetail/onsemi/NCP1117ST33T3G

But present at multiple other providers : https://octopart.com/search?q=ncp1117st33t3g&currency=USD&specs=0

Not sure that is any concern, it uses a standard SOT-223 footprint and there will be plenty of drop-in replacements if needed : https://www.digikey.com/en/products/filter/pmic/pmic-voltage-regulators-linear/699?s=N4IgjCBcpgbFoDGUBmBDANgZwKYBoQB7KAbRABYAGAVgGYAOAdhAF0CAHAFyhAGVOATgEsAdgHMQAXwLkI0EMkjps%2BIqRC1yjcrQhsQXHv2HipBMI0YBOBAtSZcBYpDIXZYaqw7dIfQaIlpcCt6G3lFZUc1FxBKViCAWgAmW0VBAFdVZzJPFkSwpCgMrPU9SXKgA

[josuah]

These results from DigiKey max out at 500mA though