unable to create gateware

[zeeshan3534]

while running the command make gateware got this error

Error:

unable to create gateware and i have already installed vivado in my system
kindly help me

[CarlFK]

Me too.

I followed these instructions
https://github.com/timvideos/litex-buildenv/wiki/HowTo-LCA2018-FPGA-Miniconf-VexRiscv-Renode

(LX P=arty C=vexriscv) juser@gator:~/tv2/litex-buildenv$ export CPU=vexriscv PLATFORM=arty TARGET=net
(LX P=arty C=vexriscv) juser@gator:~/tv2/litex-buildenv$ make gateware
mkdir -p build/arty_net_vexriscv
time python -u ./make.py --platform=arty --target=net --cpu-type=vexriscv --iprange=192.168.100     \
	2>&1 | tee -a /home/juser/tv2/litex-buildenv/build/arty_net_vexriscv/output.20220301-014213.log; (exit ${PIPESTATUS[0]})
Compat: SoCSDRAM is deprecated since 2020-03-24 and will soon no longer work, please update. Switch to SoCCore/add_sdram/soc_core_args instead...........thanks :)
INFO:SoC:        __   _ __      _  __  
INFO:SoC:       / /  (_) /____ | |/_/  
INFO:SoC:      / /__/ / __/ -_)>  <    
INFO:SoC:     /____/_/\__/\__/_/|_|  
INFO:SoC:  Build your hardware, easily!
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoC:Creating SoC... (2022-03-01 01:42:15)
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoC:FPGA device : xc7a35t-csg324-1.
INFO:SoC:System clock: 100.00MHz.
INFO:SoCBusHandler:Creating Bus Handler...
INFO:SoCBusHandler:32-bit wishbone Bus, 4.0GiB Address Space.
INFO:SoCBusHandler:Adding reserved Bus Regions...
INFO:SoCBusHandler:Bus Handler created.
INFO:SoCCSRHandler:Creating CSR Handler...
INFO:SoCCSRHandler:32-bit CSR Bus, 32-bit Aligned, 16.0KiB Address Space, 2048B Paging, big Ordering (Up to 32 Locations).
INFO:SoCCSRHandler:Adding reserved CSRs...
INFO:SoCCSRHandler:CSR Handler created.
INFO:SoCIRQHandler:Creating IRQ Handler...
INFO:SoCIRQHandler:IRQ Handler (up to 32 Locations).
INFO:SoCIRQHandler:Adding reserved IRQs...
INFO:SoCIRQHandler:IRQ Handler created.
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoC:Initial SoC:
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoC:32-bit wishbone Bus, 4.0GiB Address Space.
INFO:SoC:32-bit CSR Bus, 32-bit Aligned, 16.0KiB Address Space, 2048B Paging, big Ordering (Up to 32 Locations).
INFO:SoC:IRQ Handler (up to 32 Locations).
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoCBusHandler:io0 Region added at Origin: 0x80000000, Size: 0x80000000, Mode: RW, Cached: False Linker: False.
INFO:SoC:CPU overriding rom mapping from 0x0 to 0x0.
INFO:SoC:CPU overriding sram mapping from 0x1000000 to 0x10000000.
INFO:SoC:CPU overriding main_ram mapping from 0x40000000 to 0x40000000.
INFO:SoCBusHandler:cpu_bus0 added as Bus Master.
INFO:SoCBusHandler:cpu_bus1 added as Bus Master.
INFO:SoCBusHandler:rom Region added at Origin: 0x00000000, Size: 0x00020000, Mode: R, Cached: True Linker: False.
INFO:SoCBusHandler:rom added as Bus Slave.
INFO:SoC:RAM rom added Origin: 0x00000000, Size: 0x00020000, Mode: R, Cached: True Linker: False.
INFO:SoCBusHandler:sram Region added at Origin: 0x10000000, Size: 0x00008000, Mode: RW, Cached: True Linker: False.
INFO:SoCBusHandler:sram added as Bus Slave.
INFO:SoC:RAM sram added Origin: 0x10000000, Size: 0x00008000, Mode: RW, Cached: True Linker: False.
INFO:SoCIRQHandler:uart IRQ allocated at Location 0.
INFO:SoCIRQHandler:timer0 IRQ allocated at Location 1.
INFO:S7PLL:Creating S7PLL, speedgrade -1.
INFO:S7PLL:Registering Single Ended ClkIn of 100.00MHz.
INFO:S7PLL:Creating ClkOut0 sys of 100.00MHz (+-10000.00ppm).
INFO:S7PLL:Creating ClkOut1 sys4x of 400.00MHz (+-10000.00ppm).
INFO:S7PLL:Creating ClkOut2 sys4x_dqs of 400.00MHz (+-10000.00ppm).
INFO:S7PLL:Creating ClkOut3 clk200 of 200.00MHz (+-10000.00ppm).
INFO:S7PLL:Creating ClkOut4 eth of 25.00MHz (+-10000.00ppm).
INFO:SoCCSRHandler:ddrphy CSR allocated at Location 0.
INFO:SoCBusHandler:main_ram Region added at Origin: 0x40000000, Size: 0x10000000, Mode: RW, Cached: True Linker: False.
INFO:SoCBusHandler:main_ram added as Bus Slave.
INFO:SoCCSRHandler:info CSR allocated at Location 1.
Traceback (most recent call last):
  File "./make.py", line 185, in <module>
    main()
  File "./make.py", line 123, in main
    soc = get_soc(args, platform)
  File "./make.py", line 57, in get_soc
    soc = SoC(platform, ident=SoC.__name__, **soc_sdram_argdict(args), **dict(args.target_option))
  File "/home/juser/tv2/litex-buildenv/targets/arty/net.py", line 19, in __init__
    BaseSoC.__init__(self, platform, *args, **kwargs)
  File "/home/juser/tv2/litex-buildenv/targets/arty/base.py", line 56, in __init__
    self.submodules.cas = cas.ControlAndStatus(platform, sys_clk_freq)
  File "/home/juser/tv2/litex-buildenv/gateware/cas.py", line 98, in __init__
    self.buttons_ev.finalize()
  File "/home/juser/tv2/litex-buildenv/third_party/migen/migen/fhdl/module.py", line 157, in finalize
    self.do_finalize(*args, **kwargs)
  File "/home/juser/tv2/litex-buildenv/third_party/litex/litex/soc/interconnect/csr_eventmanager.py", line 183, in do_finalize
    self.status = CSRStatus(n, description=desc, fields=fields)
  File "/home/juser/tv2/litex-buildenv/third_party/litex/litex/soc/interconnect/csr.py", line 291, in __init__
    self.fields = CSRFieldAggregate(fields, CSRAccess.ReadOnly)
  File "/home/juser/tv2/litex-buildenv/third_party/litex/litex/soc/interconnect/csr.py", line 209, in __init__
    self.check_names(fields)
  File "/home/juser/tv2/litex-buildenv/third_party/litex/litex/soc/interconnect/csr.py", line 229, in check_names
    raise ValueError("CSRField \"{}\" name is already used in CSR register".format(field.name))
ValueError: CSRField "btn_ev" name is already used in CSR register

[CarlFK]

from #LiteX
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florent says
SoCSDRAM is now fully deprecated, so you'll won't even have the warning. I'm not sure it's worth using upstream LiteX with litex-buildenv if the project is not maintained.

I'm personally maintaining LiteX-Boards and making sure other derivated projects are also maintained, but I can't say for litex-buildenv
The equivalent of what you are trying to do with LiteX-Boards would probably be: python3 -m litex_boards.targets.digilent_arty --cpu-type=mor1kx --with-ethernet --eth-ip=192.168.1.100 --build --load

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