From dde9852d816c553003bd8446a179a7b883ba924c Mon Sep 17 00:00:00 2001
From: JiangyuanGu <31883260+JiangyuanGu@users.noreply.github.com>
Date: Mon, 31 Oct 2022 14:30:38 +0800
Subject: [PATCH] Update SpinalHDL_Chinese_Doc.md

---
 merge all/SpinalHDL_Chinese_Doc.md | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/merge all/SpinalHDL_Chinese_Doc.md b/merge all/SpinalHDL_Chinese_Doc.md
index fae2966..d5531ea 100644
--- a/merge all/SpinalHDL_Chinese_Doc.md	
+++ b/merge all/SpinalHDL_Chinese_Doc.md	
@@ -2778,8 +2778,8 @@ Verilog
     |           x >> y           |     逻辑右移, y: UInt     |    Bits(w(x) bits)     |
     |           x << y           |     逻辑左移, y: Int      |   Bits(w(x)+y bits)    |
     |           x << y           |     逻辑左移, y: UInt     | Bits(w(x)+max(y) bits) |
-    |             x|>>           |           >> y            | 逻辑右移, y: Int/UInt  | Bits(w(x) bits) |
-    |             x|<<           |           << y            | 逻辑左移, y: Int/UInt  | Bits(w(x) bits) |
+    |           x\|>>y           |           >> y            | 逻辑右移, y: Int/UInt  | Bits(w(x) bits) |
+    |           x\|<<y           |           << y            | 逻辑左移, y: Int/UInt  | Bits(w(x) bits) |
     |      x.rotateLeft(y)       | 逻辑循环左移, y: UInt/Int |    Bits(w(x) bits)     |
     |      x.rotateRight(y)      | 逻辑循环右移, y: UInt/Int |    Bits(w(x) bits)     |
     |       x.clearAll[()]       |       清除所有bits        |                        |