From 6c7447aefa03824fdd3c79b603e60cb16c74c933 Mon Sep 17 00:00:00 2001 From: Andy Ross Date: Fri, 20 Dec 2024 06:43:00 -0800 Subject: [PATCH] tools/topology1: Add basic mt8196 topology Add initial M4 topology for the mt8196 DSP Originally by Darren Ye Signed-off-by: Andy Ross --- tools/topology/topology1/CMakeLists.txt | 1 + .../topology1/platform/mediatek/mt8196.m4 | 23 +++ tools/topology/topology1/sof-mt8196-mt6681.m4 | 148 ++++++++++++++++++ 3 files changed, 172 insertions(+) create mode 100644 tools/topology/topology1/platform/mediatek/mt8196.m4 create mode 100644 tools/topology/topology1/sof-mt8196-mt6681.m4 diff --git a/tools/topology/topology1/CMakeLists.txt b/tools/topology/topology1/CMakeLists.txt index d2ddbcc70caf..c7e870b16837 100644 --- a/tools/topology/topology1/CMakeLists.txt +++ b/tools/topology/topology1/CMakeLists.txt @@ -98,6 +98,7 @@ set(TPLGS "sof-mt8186-mt6366\;sof-mt8186-mt6366-rt1019-rt5682s-waves\;-DWAVES=1" "sof-mt8188-mt6359\;sof-mt8188" "sof-mt8188-mt6359\;sof-mt8188-waves\;-DWAVES=1" + "sof-mt8196-mt6681\;sof-mt8196" "sof-acp-renoir\;sof-acp" "sof-rn-rt5682-rt1019\;sof-rn-rt5682-rt1019" diff --git a/tools/topology/topology1/platform/mediatek/mt8196.m4 b/tools/topology/topology1/platform/mediatek/mt8196.m4 new file mode 100644 index 000000000000..74cdd252f024 --- /dev/null +++ b/tools/topology/topology1/platform/mediatek/mt8196.m4 @@ -0,0 +1,23 @@ +# +# MT8196 differentiation for pipelines and components +# + +include(`memory.m4') + +define(`PLATFORM_DAI_MEM_CAP', MEMCAPS(MEM_CAP_RAM, MEM_CAP_DMA, MEM_CAP_CACHE)) +define(`PLATFORM_HOST_MEM_CAP', MEMCAPS(MEM_CAP_RAM, MEM_CAP_DMA, MEM_CAP_CACHE)) +define(`PLATFORM_PASS_MEM_CAP', MEMCAPS(MEM_CAP_RAM, MEM_CAP_DMA, MEM_CAP_CACHE)) +define(`PLATFORM_COMP_MEM_CAP', MEMCAPS(MEM_CAP_RAM, MEM_CAP_CACHE)) + +# Low Latency PCM Configuration +W_VENDORTUPLES(pipe_ll_schedule_plat_tokens, sof_sched_tokens, LIST(` ', `SOF_TKN_SCHED_MIPS "50000"')) +W_DATA(pipe_ll_schedule_plat, pipe_ll_schedule_plat_tokens) + +# Media PCM Configuration +W_VENDORTUPLES(pipe_media_schedule_plat_tokens, sof_sched_tokens, LIST(` ', `SOF_TKN_SCHED_MIPS "100000"')) +W_DATA(pipe_media_schedule_plat, pipe_media_schedule_plat_tokens) + +# DAI schedule Configuration - scheduled by IRQ +W_VENDORTUPLES(pipe_dai_schedule_plat_tokens, sof_sched_tokens, LIST(` ', `SOF_TKN_SCHED_MIPS "5000"')) +W_DATA(pipe_dai_schedule_plat, pipe_dai_schedule_plat_tokens) + diff --git a/tools/topology/topology1/sof-mt8196-mt6681.m4 b/tools/topology/topology1/sof-mt8196-mt6681.m4 new file mode 100644 index 000000000000..e52c8c84fa0e --- /dev/null +++ b/tools/topology/topology1/sof-mt8196-mt6681.m4 @@ -0,0 +1,148 @@ +# +# Topology for MT8196 board with mt6681 +# + +# Include topology builder +include(`utils.m4') +include(`dai.m4') +include(`pipeline.m4') +include(`afe.m4') +include(`pcm.m4') +include(`buffer.m4') + +# Include TLV library +include(`common/tlv.m4') + +# Include Token library +include(`sof/tokens.m4') + +# Include DSP configuration +include(`platform/mediatek/mt8196.m4') + +# +# Define the pipelines +# +# PCM0 ---> AFE (Speaker - nau8318) +# PCM1 ---> AFE (Headset playback - nau88l25) +# PCM2 <--- AFE (DMIC0 - AP) +# PCM3 <--- AFE (Headset record - nau88l25) +# PCM4 <--- AFE (DMIC1 - AP) + +dnl PIPELINE_PCM_ADD(pipeline, +dnl pipe id, pcm, max channels, format, +dnl period, priority, core, +dnl pcm_min_rate, pcm_max_rate, pipeline_rate, +dnl time_domain, sched_comp) + +define(`ENDPOINT_NAME', `Speakers') +# Low Latency playback pipeline 1 on PCM 16 using max 2 channels of s16le +# Set 1000us deadline with priority 0 on core 0 +PIPELINE_PCM_ADD(ifdef(`WAVES', sof/pipe-waves-codec-playback.m4, sof/pipe-passthrough-playback.m4), + 1, 0, 2, s16le, + 1000, 0, 0, + 48000, 48000, 48000) +undefine(`ENDPOINT_NAME') + +define(`ENDPOINT_NAME', `Headphones') +# Low Latency playback pipeline 2 on PCM 17 using max 2 channels of s16le +# Set 1000us deadline with priority 0 on core 0 +PIPELINE_PCM_ADD(ifdef(`WAVES', sof/pipe-waves-codec-playback.m4, sof/pipe-passthrough-playback.m4), + 2, 1, 2, s16le, + 1000, 0, 0, + 48000, 48000, 48000) +undefine(`ENDPOINT_NAME') +# Low Latency capture pipeline 3 on PCM 18 using max 2 channels of s16le +# Set 2000us deadline with priority 0 on core 0 +PIPELINE_PCM_ADD(sof/pipe-passthrough-capture.m4, + 3, 2, 2, s16le, + 2000, 0, 0, + 48000, 48000, 48000) + +# Low Latency capture pipeline 4 on PCM 19 using max 2 channels of s16le +# Set 2000us deadline with priority 0 on core 0 +PIPELINE_PCM_ADD(sof/pipe-passthrough-capture.m4, + 4, 3, 2, s16le, + 2000, 0, 0, + 48000, 48000, 48000) + +# Low Latency capture pipeline 4 on PCM 20 using max 2 channels of s16le +# Set 2000us deadline with priority 0 on core 0 +PIPELINE_PCM_ADD(sof/pipe-passthrough-capture.m4, + 5, 4, 2, s16le, + 2000, 0, 0, + 48000, 48000, 48000) + + + +# +# DAIs configuration +# + +dnl DAI_ADD(pipeline, +dnl pipe id, dai type, dai_index, dai_be, +dnl buffer, periods, format, +dnl deadline, priority, core) + + +# playback DAI is AFE using 2 periods +# Buffers use s16le format, with 48 frame per 1000us on core 0 with priority 0 +DAI_ADD(sof/pipe-dai-playback.m4, + 1, AFE, 0, AFE_SOF_DL_24CH, + PIPELINE_SOURCE_1, 2, s16le, + 1000, 0, 0, SCHEDULE_TIME_DOMAIN_TIMER) + +# playback DAI is AFE using 2 periods +# Buffers use s16le format, with 48 frame per 1000us on core 0 with priority 0 +DAI_ADD(sof/pipe-dai-playback.m4, + 2, AFE, 1, AFE_SOF_DL1, + PIPELINE_SOURCE_2, 2, s16le, + 1000, 0, 0, SCHEDULE_TIME_DOMAIN_TIMER) +# capture DAI is AFE using 2 periods +# Buffers use s16le format, with 48 frame per 2000us on core 0 with priority 0 +DAI_ADD(sof/pipe-dai-capture.m4, + 3, AFE, 2, AFE_SOF_UL0, + PIPELINE_SINK_3, 2, s16le, + 2000, 0, 0, SCHEDULE_TIME_DOMAIN_TIMER) + +# capture DAI is AFE using 2 periods +# Buffers use s16le format, with 48 frame per 2000us on core 0 with priority 0 +DAI_ADD(sof/pipe-dai-capture.m4, + 4, AFE, 3, AFE_SOF_UL1, + PIPELINE_SINK_4, 2, s16le, + 2000, 0, 0, SCHEDULE_TIME_DOMAIN_TIMER) + +# capture DAI is AFE using 2 periods +# Buffers use s16le format, with 48 frame per 2000us on core 0 with priority 0 +DAI_ADD(sof/pipe-dai-capture.m4, + 5, AFE, 4, AFE_SOF_UL2, + PIPELINE_SINK_5, 2, s16le, + 2000, 0, 0, SCHEDULE_TIME_DOMAIN_TIMER) + +#SCHEDULE_TIME_DOMAIN_DMA +dnl PCM_PLAYBACK_ADD(name, pcm_id, playback) + +# PCM Low Latency, id 0 +PCM_PLAYBACK_ADD(SOF_DL_24CH, 0, PIPELINE_PCM_1) +PCM_PLAYBACK_ADD(SOF_DL1, 1, PIPELINE_PCM_2) +PCM_CAPTURE_ADD(SOF_UL0, 2, PIPELINE_PCM_3) +PCM_CAPTURE_ADD(SOF_UL1, 3, PIPELINE_PCM_4) +PCM_CAPTURE_ADD(SOF_UL2, 4, PIPELINE_PCM_5) + + +dnl DAI_CONFIG(type, dai_index, link_id, name, afe_config) + +DAI_CONFIG(AFE, 0, 0, AFE_SOF_DL_24CH, + AFE_CONFIG(AFE_CONFIG_DATA(AFE, 0, 48000, 2, s16le))) + +DAI_CONFIG(AFE, 1, 0, AFE_SOF_DL1, + AFE_CONFIG(AFE_CONFIG_DATA(AFE, 1, 48000, 2, s16le))) + +DAI_CONFIG(AFE, 2, 0, AFE_SOF_UL0, + AFE_CONFIG(AFE_CONFIG_DATA(AFE, 2, 48000, 2, s16le))) + +DAI_CONFIG(AFE, 3, 0, AFE_SOF_UL1, + AFE_CONFIG(AFE_CONFIG_DATA(AFE, 3, 48000, 2, s16le))) + +DAI_CONFIG(AFE, 4, 0, AFE_SOF_UL2, + AFE_CONFIG(AFE_CONFIG_DATA(AFE, 4, 48000, 2, s16le))) +