diff --git a/CHANGELOG.md b/CHANGELOG.md index 5dc4c57a..6dff0247 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -18,6 +18,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/). ### Changed - Use `stm32f4-staging` until `stm32f4` is released [#706] + - RTIC2 monotonics fix: CC1 instead of CC3 - Allow different lengths of buffers in hal_1 SpiBus impl [#566] [#566]: https://github.com/stm32-rs/stm32f4xx-hal/pull/566 diff --git a/Cargo.toml b/Cargo.toml index 6c83cce0..79d7ce22 100644 --- a/Cargo.toml +++ b/Cargo.toml @@ -679,7 +679,7 @@ required-features = ["tim2", "rtic1"] [[example]] name = "rtic2-tick" -required-features = ["rtic2", "rtic-tim2"] +required-features = ["rtic2", "rtic-tim3"] [[example]] name = "rtic-usart-shell" diff --git a/examples/rtic2-tick.rs b/examples/rtic2-tick.rs index 0f023de2..930c8f50 100644 --- a/examples/rtic2-tick.rs +++ b/examples/rtic2-tick.rs @@ -10,7 +10,7 @@ use stm32f4xx_hal::{ pac, prelude::*, }; -type Mono = stm32f4xx_hal::timer::MonoTimerUs; +type Mono = stm32f4xx_hal::timer::MonoTimerUs; // Uncomment if use SysTick as monotonic timer //use rtic_monotonics::systick::prelude::*; @@ -35,8 +35,8 @@ mod app { let rcc = ctx.device.RCC.constrain(); let clocks = rcc.cfgr.sysclk(48.MHz()).freeze(); - // Create TIM2 monotonic and initialize timer queue - ctx.device.TIM2.monotonic_us(&mut ctx.core.NVIC, &clocks); + // Create TIM3 monotonic and initialize timer queue + ctx.device.TIM3.monotonic_us(&mut ctx.core.NVIC, &clocks); // Uncomment if use SysTick as monotonic timer //Mono::start(ctx.core.SYST, 48_000_000); diff --git a/src/timer/monotonics.rs b/src/timer/monotonics.rs index add51d65..e2316025 100644 --- a/src/timer/monotonics.rs +++ b/src/timer/monotonics.rs @@ -165,9 +165,9 @@ macro_rules! make_timer { // Configure and enable half-period interrupt self.tim - .ccr(2) + .ccr1() .write(|w| w.ccr().set(($bits::MAX - ($bits::MAX >> 1)).into())); - self.tim.dier().modify(|_, w| w.cc3ie().set_bit()); + self.tim.dier().modify(|_, w| w.cc1ie().set_bit()); // Trigger an update event to load the prescaler value to the clock. self.tim.egr().write(|w| w.ug().set_bit()); @@ -206,7 +206,7 @@ macro_rules! make_timer { fn now() -> Self::Ticks { calculate_now( || $overflow.load(Ordering::Relaxed), - || Self::tim().cnt().read().bits(), + || Self::tim().cnt().read().cnt().bits(), ) } @@ -214,7 +214,7 @@ macro_rules! make_timer { let now = Self::now(); // Since the timer may or may not overflow based on the requested compare val, we check how many ticks are left. - // `wrapping_sup` takes care of the u64 integer overflow special case. + // `wrapping_sub` takes care of the u64 integer overflow special case. let val = if instant.wrapping_sub(now) <= ($bits::MAX as u64) { instant as $bits } else { @@ -222,7 +222,7 @@ macro_rules! make_timer { 0 }; - Self::tim().ccr(1).write(|r| r.ccr().set(val.into())); + Self::tim().ccr2().write(|r| r.ccr().set(val.into())); } fn clear_compare_flag() { @@ -249,8 +249,8 @@ macro_rules! make_timer { assert!(prev % 2 == 1, "Monotonic must have missed an interrupt!"); } // Half period - if Self::tim().sr().read().cc3if().bit_is_set() { - Self::tim().sr().modify(|_, w| w.cc3if().clear_bit()); + if Self::tim().sr().read().cc1if().bit_is_set() { + Self::tim().sr().modify(|_, w| w.cc1if().clear_bit()); let prev = $overflow.fetch_add(1, Ordering::Relaxed); assert!(prev % 2 == 0, "Monotonic must have missed an interrupt!"); } @@ -273,7 +273,7 @@ make_timer!(tim3, TIM3, u16, TIMER3_OVERFLOWS, TIMER3_TQ); make_timer!(tim4, TIM4, u16, TIMER4_OVERFLOWS, TIMER4_TQ); #[cfg(all(feature = "tim5", feature = "rtic-tim5"))] -make_timer!(tim5, TIM5, u16, TIMER5_OVERFLOWS, TIMER5_TQ); +make_timer!(tim5, TIM5, u32, TIMER5_OVERFLOWS, TIMER5_TQ); pub trait Irq { const IRQ: pac::Interrupt;