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Memory bus width #21

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dhslichter opened this issue Jan 29, 2020 · 1 comment
Closed

Memory bus width #21

dhslichter opened this issue Jan 29, 2020 · 1 comment

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@dhslichter
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Previous issues with DMA slowness on Kasli (m-labs/artiq#946) suggest that it would be helpful to make the memory bus wider. If Kasli-SOC is to be a higher-performance sibling of Kasli, it seems we should think about a wider memory bus (more like KC705)?

@filipswit
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Not sure what we can do with it. On KC705 bus is x64. In Kasli-SOC we connect RAM to PS only, so we have x32.

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