v1.0 issues

[jordens]

@gkasprow Maria mentioned that prototype tests showed the need for improvement and a revision is being done. Could you summarize and update the repo?

[gkasprow]

The existing version works but has stability issues when working with capacitive loads. It needs fine-tuning of compensation capacitors.
We are working on a ~10x less noisy version for high-voltage ion traps, but that will take some time. Since low noise amps usually work with <40V, we need to implement some bootstrap techniques and use other amps. There is also a visible peak from DC/DC converters; we are testing alternate ones and better LDOs.
So, it depends on your needs; if you need sth fancy with very low noise, wait for the new design.
If you can live with the existing design, you can use it as it is.

[evilmav]

@gkasprow
I am curious how the technique is going to work in terms of the feedback resistor noise - I'm yet to find a solution which wouldn't negate the advantages of the bootstrapped low input noise opamp without drawing ridiculous powers.

One thing we do in our own design is making differential amplifiers out of ltc6090-5 with respect to an external ground provided from the cable, which should be broadband enough suppress 50hz hum from the potential ground loop over the shielding etc to sinara's ground. The external ground is buffered with a high-speed amplifier to avoid crosstalk due to the common impedance over the constantan wires.

Another thing we are currently considering: there are use cases where we want to inject hundreds of kHz up to a few MHz range signals into the output (at a limited swing only). Due to the DMA limitations of the Kasli, Fastino fails to generate a sustained sine even at tens of kHz. We were thinking about adding further inputs to the differential amplifiers to connect them to the Urukul to be able to superimpose these frequencies, with LTC6090-5 maybe being just barely fast enough to do.. I'm worried about crosstalk though...

[jordens]

Due to the m-labs/artiq#1423, Fastino fails to generate a sustained sine even at tens of kHz.

This is a bit misleading. This isn't really designed to sustain high sample rates. On the contrary: the idea is to use an efficient parametrization of the samples such that large amounts of samples are not needed. Adding one or even a few DDS to the Fastino gateware can be muxed onto channels wouldn't be hard. Just needs proper design work.

The idea of an external ground reference for Zotino/Fastino etc is a good one. That has been done before. But AFAICT the reference buffer doesn't need to be (significantly) faster than the channel driver.
You still need to take proper care of the current return path though.

[evilmav]

This is misleading. This isn't really designed to sustain high sample rates. On the contrary: the idea is to use an efficient parametrization of the samples such that large amounts of samples are not needed. Adding one or even a few DDS to the Fastino gateware can be muxed onto channels wouldn't be hard. Just needs proper design work.

I agree, but it seems yet to be implemented. We've actually hoped to gain improvement through better DMA on Kasli SoC but it seems to have created random complete lockups of the gateware either...
Anyway, our upper frequencies are pushing the Nyquist frequency of the Fastino anyway, so it can not fully replace the Urukul injection...

[gkasprow]

we installed C1=5.6pF and amplifier is stable now.