18.2 Compressed Instruciton Formats new format CA and field funct6 - is it in core or as Zc extension only?

[apws]

(I tried to post new issue, but it failed)

In current riscv-spec.pdf I see in chapter 18.2 Compressed Instruciton Formats new format CA which is not used in entire document more, I only found some "Zc" (proposed) extension with some new compressed instructions but I dont know how this relates to base RV32I/C or even RV32E - is this expected to be in core or really only as extension? I chatted now with GPT about ISA and it doesnt know this and I myself was confused reading latest spec and having new funct6 field there... BTW is somewhere noted which specs versions was used to design say, ESP32-C3 to know what is supported there, as example? Or is such tiny chip smart enough to report itself by CSR any capabilities? I am working on simple RV32E based interpreter only, trying to stick to some CORE features only, without extensions, simply RV32EMC or so ....

[apws]

Zc is noted only here, not in this ISA manual, as far as I searched ...
https://github.com/riscv/riscv-code-size-reduction/blob/main/Zc-specification/changes_since_v0.50.adoc

[nick-knight]

The C extension provides a collection of 16-bit instructions. It has existed since the early days of the ISA. Later on, there was an effort to expand the scope of the C extension: this led to the Zc{a,f,d,b,cmp,cmt} extensions. These extensions are all defined in the same document; the latest draft is here: https://github.com/riscv/riscv-code-size-reduction/releases

[apws]

thanks, and I also realized that I missed usage of CA format in ISA manual ... anyway, decoder for this is far more complex that 32bit thing how I am considering it, so I will completely omit this from runtime. Its mostly for learning and small tasks on even smallest MCUs... will see

[allenjbaum]

The other part of the question was: "somewhere noted which specs versions was used to design say, ESP32-C3 to know what is supported there, as example? Or is such tiny chip smart enough to report itself by CSR any capabilities? " Implementors are not required to list anything - but to get the RISC-V branding, they need to pass the architectural tests, and to do that they need to provide a YAML formatted file that describes precisely which features they areimplementing. That might not help if they decide not to claim something they are implementing, of course. Software may also need to discover which features are implemented. The MISA CSR can give some hints, but it was outgrown almost immediately; very few extensions will show anything in MISA from here forward. There is a Unified Discovery extension which is being developed. When it is fully fleshed out, a hart can interrogate a CSR which points to a data structure that describes features that are supported by the hart (though not necessarily all).

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On Sat, Mar 25, 2023 at 7:34 AM Nick Knight ***@***.***> wrote: The C extension provides a collection of 16-bit instructions. It has existed since the early days of the ISA. Later on, there was an effort to expand the scope of the C extension: this led to the Zc{a,f,d,b,cmp,cmt} extensions. These extensions are all defined in the same document; the latest draft is here: https://github.com/riscv/riscv-code-size-reduction/releases — Reply to this email directly, view it on GitHub <#999 (reply in thread)>, or unsubscribe <https://github.com/notifications/unsubscribe-auth/AHPXVJVHU3M2L2QFZH64ONTW5367XANCNFSM6AAAAAAWHRB4RU> . You are receiving this because you are subscribed to this thread.Message ID: ***@***.*** com>